vinodsake / NAND-Flash-Memory-Controller-verification
☆41Updated 8 years ago
Alternatives and similar repositories for NAND-Flash-Memory-Controller-verification:
Users that are interested in NAND-Flash-Memory-Controller-verification are comparing it to the libraries listed below
- AXI Interface Nand Flash Controller (Sync mode)☆91Updated 8 months ago
- PCIE 5.0 Graduation project (Verification Team)☆68Updated last year
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆53Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 11 months ago
- UART -> AXI Bridge☆61Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- ☆58Updated 2 years ago
- UART design in SV and verification using UVM and SV☆43Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆17Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- round robin arbiter☆72Updated 10 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Implementation of the PCIe physical layer☆37Updated 3 months ago
- ☆36Updated 9 years ago
- Verilog Ethernet Switch (layer 2)☆43Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆55Updated 8 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- ☆50Updated 2 years ago