StanfordAHA / AhaM3SoC
SoC Based on ARM Cortex-M3
☆27Updated last month
Alternatives and similar repositories for AhaM3SoC:
Users that are interested in AhaM3SoC are comparing it to the libraries listed below
- ☆16Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆18Updated 7 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆29Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆43Updated 11 months ago
- AXI Interconnect☆47Updated 3 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆15Updated 3 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- ☆24Updated 3 years ago
- UART design in SV and verification using UVM and SV☆39Updated 5 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆22Updated 11 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆45Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- ☆20Updated 5 years ago
- Verification IP for AMBA APB Protocol☆28Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- Implementation of the PCIe physical layer☆33Updated last month
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆33Updated 4 years ago
- Sample UVM code for axi ram dut☆30Updated 3 years ago
- System on Chip verified with UVM/OSVVM/FV☆23Updated last month
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆29Updated 4 years ago