StanfordAHA / AhaM3SoC
SoC Based on ARM Cortex-M3
☆28Updated last week
Alternatives and similar repositories for AhaM3SoC:
Users that are interested in AhaM3SoC are comparing it to the libraries listed below
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- verification of simple axi-based cache☆18Updated 5 years ago
- ☆21Updated 5 years ago
- ☆19Updated 2 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- AXI Interconnect☆47Updated 3 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆15Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- System on Chip verified with UVM/OSVVM/FV☆23Updated last month
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- ☆31Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆49Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆34Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆34Updated 2 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- This is the repository for the IEEE version of the book☆57Updated 4 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- ☆25Updated 3 years ago
- UART design in SV and verification using UVM and SV☆40Updated 5 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- Verification IP for AMBA APB Protocol☆28Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 10 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- Verification IP for APB protocol☆59Updated 4 years ago