StanfordAHA / AhaM3SoCLinks
SoC Based on ARM Cortex-M3
☆33Updated 3 months ago
Alternatives and similar repositories for AhaM3SoC
Users that are interested in AhaM3SoC are comparing it to the libraries listed below
Sorting:
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆64Updated last year
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- ☆20Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆22Updated last year
- AXI Interconnect☆52Updated 4 years ago
- ☆61Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 8 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- Verification IP for APB protocol☆69Updated 4 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- ☆26Updated 4 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆20Updated last year
- ☆35Updated 6 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- UART design in SV and verification using UVM and SV☆49Updated 5 years ago
- Verification IP for AMBA APB Protocol☆30Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆25Updated 7 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- Sample UVM code for axi ram dut☆38Updated 3 years ago