StanfordAHA / AhaM3SoCLinks
SoC Based on ARM Cortex-M3
☆32Updated 2 months ago
Alternatives and similar repositories for AhaM3SoC
Users that are interested in AhaM3SoC are comparing it to the libraries listed below
Sorting:
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- General Purpose AXI Direct Memory Access☆55Updated last year
- ☆20Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated 2 weeks ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 2 years ago
- AXI Interconnect☆51Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆59Updated 2 years ago
- ☆34Updated 6 years ago
- ☆26Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 6 months ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Verification IP for APB protocol☆68Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 2 years ago
- Implementation of the PCIe physical layer☆47Updated 3 weeks ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆60Updated last year
- ☆21Updated 5 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆67Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆19Updated 7 years ago