StanfordAHA / AhaM3SoCLinks
SoC Based on ARM Cortex-M3
☆33Updated 4 months ago
Alternatives and similar repositories for AhaM3SoC
Users that are interested in AhaM3SoC are comparing it to the libraries listed below
Sorting:
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- General Purpose AXI Direct Memory Access☆59Updated last year
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 8 months ago
- ☆20Updated 2 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- ☆36Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆40Updated 3 years ago
- AXI Interconnect☆53Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆66Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- ☆64Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆27Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- Verification IP for APB protocol☆69Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆26Updated 3 years ago
- AXI4 BFM in Verilog☆33Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Sample UVM code for axi ram dut☆37Updated 3 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- round robin arbiter☆75Updated 11 years ago
- ☆26Updated 4 years ago