StanfordAHA / AhaM3SoCLinks
SoC Based on ARM Cortex-M3
☆32Updated last month
Alternatives and similar repositories for AhaM3SoC
Users that are interested in AhaM3SoC are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆53Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- AXI Interconnect☆50Updated 3 years ago
- Implementation of the PCIe physical layer☆44Updated 2 months ago
- ☆20Updated 2 years ago
- ☆34Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated 11 months ago
- ☆25Updated 4 years ago
- ☆29Updated 4 years ago
- ☆56Updated 2 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- System on Chip verified with UVM/OSVVM/FV☆29Updated last month
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 6 months ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 5 months ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 3 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆64Updated 4 years ago