Alternatives and similar repositories for MMC:

Users that are interested in MMC are comparing it to the libraries listed below

• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆32Updated 3 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆21Updated 6 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆36Updated 8 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆18Updated 5 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆63Updated 3 years ago
• yedk / arm_cortex_m0_xillinx
  基于arm cortex-m0内核的xillinx fpga sopc工程项目
  ☆12Updated 5 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆33Updated 4 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆36Updated 2 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• BigPig-Bro / Gowin
  【例程】国产高云FPGA 开发板及其工程
  ☆26Updated 5 months ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆43Updated last year
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆46Updated 4 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• Frogwells / fpga_cmos_design
  这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西
  ☆33Updated 7 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆12Updated 6 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 5 years ago
• DeamonYang / FPGA_SYNC_ASYNC_FIFO
  FPGA 同步FIFO与异步FIFO
  ☆29Updated 6 years ago
• huhuikevin / i2c_slave
  fpga i2c slave verilog hdl rtl
  ☆13Updated 9 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆54Updated 8 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆30Updated 6 years ago
• freecores / robust_axi2ahb
  Generic AXI to AHB bridge
  ☆16Updated 10 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆31Updated 2 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆28Updated 3 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆18Updated 6 years ago
• lucky-wfw / IC_System_Design
  Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …
  ☆27Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• aq12138 / Git_Bilbili
  verilog
  ☆21Updated last year