MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计
☆21May 24, 2023Updated 3 years ago
Alternatives and similar repositories for MMC
Users that are interested in MMC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 7 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated last year
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 8 months ago
- practice configure AHB-Lite bus protocol☆20Mar 11, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 【2022集创赛】Arm杯一等奖作品：Cortex-M0智能娱乐收音机 开源项目☆28Mar 21, 2023Updated 3 years ago
- 帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目☆11May 15, 2022Updated 4 years ago
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆30Apr 29, 2024Updated 2 years ago
- ☆14Jun 30, 2019Updated 7 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Version 2.1 of the U.S. Navy Long Wave Propagation Capability code with alterations for running as a MATLAB function. The altered version…☆19Oct 13, 2016Updated 9 years ago
- ☆13Nov 13, 2022Updated 3 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated last year
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 14 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- ☆10Jan 30, 2017Updated 9 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆215Aug 23, 2023Updated 2 years ago
- LiteX based FPGA gateware for Thunderscope.☆30Apr 21, 2026Updated 3 months ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- USB-Blaster instance on CH55x MCU.☆59Jul 8, 2019Updated 7 years ago
- 8051 core☆113Jul 17, 2014Updated 12 years ago
- ☆11May 24, 2019Updated 7 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Step by step tutorial for building CortexM0 SoC☆41Mar 29, 2022Updated 4 years ago
- Boost library subset for FireBreath☆13Apr 17, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Open Source Cell Library for Predictive CNFET Technology☆15Mar 12, 2026Updated 4 months ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…☆42Dec 24, 2020Updated 5 years ago
- A CNN-based hardware digit/image recognition module designed on PyTorch and then implemented with Verilog on FPGA☆22Oct 17, 2022Updated 3 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- A project implementing the CORDIC algorithm for computing cosines and sines using fixed-point decimals in Verilog code（使用定点小数在 verilog 代码…☆11Aug 19, 2023Updated 2 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago