wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
☆18Updated 2 years ago
Alternatives and similar repositories for Sram-controller-design-based-on-AHB-bus:
Users that are interested in Sram-controller-design-based-on-AHB-bus are comparing it to the libraries listed below
- ☆14Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- ☆19Updated 2 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆12Updated 2 years ago
- ☆25Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆10Updated 2 years ago
- ☆36Updated 9 years ago
- An uvm verification env for ahb2apb bridge☆48Updated 3 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆19Updated 8 months ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆11Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆20Updated 2 years ago
- DDR3 function verification environment in UVM☆23Updated 6 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆12Updated 3 years ago
- ☆9Updated 4 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- AXI Interconnect☆47Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- ☆12Updated 9 years ago
- soc integration script and integration smoke script☆21Updated 2 years ago
- UVM Testbench for synchronus fifo☆16Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆22Updated 5 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago