Alternatives and similar repositories for Sram-controller-design-based-on-AHB-bus

Users that are interested in Sram-controller-design-based-on-AHB-bus are comparing it to the libraries listed below

• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆16Updated 3 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• Jon3Y / AMBA
  AHB/APB SRAM Inf, VCS&Verdi Sim.
  ☆14Updated 3 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆20Updated 12 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 11 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆19Updated 5 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• alireza-shirzad / Cordic_tanh
  Verilog and matlab implementation of tanh using Cordic algorithm
  ☆11Updated 5 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆35Updated 2 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆37Updated 10 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆53Updated 4 years ago
• MilanKubavat / TestbenchGenerator
  Generate SystemVerilog/UVM block level testbench setup with python script
  ☆10Updated 8 years ago
• mfkiwl / E203_dma
  ☆10Updated 5 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆25Updated 7 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆48Updated 2 months ago
• shalan / MS_DMAC_AHBL
  A Direct Memory Access Controller (DMAC) with AHB-lite bus interface
  ☆15Updated last year
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆13Updated 2 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆23Updated 3 years ago
• marshall-999 / UVMReference
  This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
  ☆14Updated 4 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆17Updated 5 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆14Updated 5 years ago
• zhouzaixin / arm_soc
  ☆14Updated 6 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 7 years ago