wbbbbbb123 / Sram-controller-design-based-on-AHB-busLinks
☆20Updated 3 years ago
Alternatives and similar repositories for Sram-controller-design-based-on-AHB-bus
Users that are interested in Sram-controller-design-based-on-AHB-bus are comparing it to the libraries listed below
Sorting:
- ☆16Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- ☆26Updated 4 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- ☆12Updated 10 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆18Updated 11 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- Verification IP for SPI protocol☆20Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 2 years ago
- ☆20Updated 3 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆28Updated last year
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆15Updated last year
- ☆10Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- ☆38Updated 10 years ago
- soc integration script and integration smoke script☆24Updated 3 years ago
- 异步FIFO的内部实现☆25Updated 7 years ago
- ☆17Updated 10 years ago
- AXI Interconnect☆54Updated 4 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆14Updated 4 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Updated 8 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆15Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 10 months ago