wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
☆18Updated 2 years ago
Alternatives and similar repositories for Sram-controller-design-based-on-AHB-bus:
Users that are interested in Sram-controller-design-based-on-AHB-bus are comparing it to the libraries listed below
- ☆14Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆19Updated 5 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆12Updated 2 years ago
- ☆16Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆10Updated 4 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- ☆23Updated 3 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆11Updated 3 months ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆28Updated 2 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆10Updated 3 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆15Updated 6 months ago
- 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆20Updated 2 years ago
- ☆35Updated 9 years ago
- ☆9Updated 4 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆47Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆22Updated 2 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- ☆12Updated 9 years ago
- ☆17Updated 9 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆24Updated 4 years ago
- DDR3 function verification environment in UVM☆22Updated 6 years ago
- ☆36Updated last year
- 异步FIFO的内部实现☆24Updated 6 years ago