Alternatives and similar repositories for Communication_Design

Users that are interested in Communication_Design are comparing it to the libraries listed below

• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆23Updated 5 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆45Updated 2 months ago
• chinkwo / FPGA-multiboot
  通过SPI协议实现FPGA multiboot在线升级功能
  ☆11Updated 7 years ago
• DeamonYang / FPGA_SDR
  软件无线电，使用FPGA进行正交解调。
  ☆22Updated 6 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆18Updated 6 years ago
• NingHeChuan / Digital_Front_End_Verilog
  ☆23Updated 5 years ago
• antmicro / openssd-nvme
  ☆25Updated 4 years ago
• yedk / arm_cortex_m0_xillinx
  基于arm cortex-m0内核的xillinx fpga sopc工程项目
  ☆13Updated 6 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆30Updated 3 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• maxs-well / FIR_Implementation
  FIR filter implementation
  ☆27Updated 5 years ago
• maxs-well / ad7606-driver-verilog
  AD7606 driver verilog
  ☆42Updated 6 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆20Updated 6 years ago
• xkw168 / Digital-recognition
  digital recognition base on FPGA
  ☆14Updated 5 years ago
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆66Updated 3 years ago
• txzing / modbus_crc_verilog
  FPGA纯逻辑实现modbus通信
  ☆20Updated 2 years ago
• ganyunhan / DUAL-OV5640-for-GOWIN
  A dual-camera based on OminiVison 5460 for GoWin GW2A-55K Combat Board
  ☆33Updated 3 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆50Updated 2 years ago
• caicaicai-ji / QSPI_FOR_SOC
  QSPI for SoC
  ☆22Updated 5 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 10 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 5 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆36Updated 4 years ago
• xycfwrj / zynq_axi_ddr_barebone
  minimal code to access ps DDR from PL
  ☆20Updated 5 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆36Updated 3 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆77Updated 5 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• xiesicong / Cortex_m0
  Cortex_m0软核源码，可以在FPGA上直接跑，包含UART、定时器这些外设，可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书
  ☆23Updated 4 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆71Updated 3 years ago
• sunzhengyuan / auto_simulate
  Automatic Verilog/SystemVerilog verification platform generation, support for one-click simulation
  ☆12Updated 5 years ago
• panicmarvin / cmsdk_ahb_busmatrix
  practice configure AHB-Lite bus protocol
  ☆13Updated 6 years ago