PyFive-RISC-V / pyfive_top_202011
Top level for the November shuttle
☆11Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for pyfive_top_202011
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆19Updated 4 years ago
- A padring generator for ASICs☆22Updated last year
- USB virtual model in C++ for Verilog☆28Updated last month
- RISC-V Processor written in Amaranth HDL☆33Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 5 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆20Updated last year
- A reconfigurable logic circuit made of identical rotatable tiles.☆20Updated 3 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 3 years ago
- ☆36Updated 2 years ago
- ☆33Updated last year
- XTRX LiteX/LitePCIe based design for Julia Computing☆24Updated 8 months ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Benchmarks for Yosys development☆22Updated 4 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 2 years ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- KLayout technology files for ASAP7 FinFET educational process☆18Updated last year
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆29Updated 4 years ago
- sample VCD files☆36Updated 9 months ago
- SAR ADC on tiny tapeout☆35Updated last week
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- A pipelined RISC-V processor☆47Updated 11 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆20Updated 3 years ago
- ☆29Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆44Updated this week
- Experiments with Yosys cxxrtl backend☆47Updated 10 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago
- ☆39Updated last year