Alternatives and similar repositories for pyfive_top_202011

Users that are interested in pyfive_top_202011 are comparing it to the libraries listed below

• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 4 years ago
• wyvernSemi / usbModel
  USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL
  ☆32Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆23Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 3 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆22Updated 6 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 5 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆51Updated 3 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 6 months ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆34Updated last year
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated 4 months ago
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last week
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 6 years ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆59Updated 2 months ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆32Updated last week
• AL-255 / Project-Yatsuhashi-Chip1
  ☆38Updated 3 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated last week
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆110Updated this week
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆32Updated 5 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆37Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆32Updated 3 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆34Updated 2 months ago
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆54Updated last month
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆32Updated last year
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago