Alternatives and similar repositories for pyfive_top_202011:

Users that are interested in pyfive_top_202011 are comparing it to the libraries listed below

• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆36Updated 3 years ago
• cloudxcc / Arduissimo
  Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).
  ☆20Updated 5 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 3 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆24Updated last year
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆22Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 4 years ago
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Updated 3 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 6 months ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆49Updated 2 weeks ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆37Updated 2 months ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆25Updated 5 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆20Updated 3 years ago
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆30Updated 11 months ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 2 weeks ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• enjoy-digital / xtrx_julia
  XTRX LiteX/LitePCIe based design for Julia Computing
  ☆26Updated 10 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆15Updated 10 months ago
• mattvenn / gtkwave-python-filter-process
  ☆32Updated 3 years ago
• Blinkinlabs / QL-EOS-S3-breakout
  ☆12Updated 3 years ago
• bieganski / mtkcpu
  RISC-V CPU implementation in Amaranth HDL (aka nMigen)
  ☆28Updated 5 months ago