tukl-msd / DRAMSys
DRAMSys a SystemC TLM-2.0 based DRAM simulator.
☆250Updated last week
Alternatives and similar repositories for DRAMSys:
Users that are interested in DRAMSys are comparing it to the libraries listed below
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆265Updated 4 months ago
- SystemC/TLM-2.0 Co-simulation framework☆238Updated 5 months ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆357Updated 7 months ago
- ☆131Updated last month
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆180Updated 4 years ago
- A Chisel RTL generator for network-on-chip interconnects☆189Updated 2 weeks ago
- Modeling Architectural Platform☆180Updated last week
- Network on Chip Simulator☆260Updated last year
- RISC-V SystemC-TLM simulator☆299Updated 3 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆145Updated 2 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆306Updated 3 months ago
- An AXI4 crossbar implementation in SystemVerilog☆138Updated last month
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆103Updated last week
- A modeling library with virtual components for SystemC and TLM simulators☆146Updated this week
- Vector processor for RISC-V vector ISA☆116Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆184Updated this week
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆230Updated 2 years ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆412Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Comment on the rocket-chip source code☆174Updated 6 years ago
- Fast and accurate DRAM power and energy estimation tool☆151Updated last week
- GPGPU supporting RISCV-V, developed with verilog HDL☆88Updated last month
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆163Updated 4 months ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆165Updated this week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆191Updated last week
- A matrix extension proposal for AI applications under RISC-V architecture☆132Updated last month
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆210Updated 4 years ago
- BookSim 2.0☆313Updated 9 months ago
- RiVEC Bencmark Suite☆113Updated 3 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆156Updated this week