tukl-msd / DRAMSys
DRAMSys a SystemC TLM-2.0 based DRAM simulator.
☆264Updated last month
Alternatives and similar repositories for DRAMSys:
Users that are interested in DRAMSys are comparing it to the libraries listed below
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆365Updated 9 months ago
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆184Updated 4 years ago
- SystemC/TLM-2.0 Co-simulation framework☆240Updated 6 months ago
- RISC-V SystemC-TLM simulator☆304Updated 4 months ago
- ☆153Updated last week
- Network on Chip Simulator☆269Updated last year
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆268Updated 2 weeks ago
- Modeling Architectural Platform☆187Updated last week
- A Chisel RTL generator for network-on-chip interconnects☆196Updated this week
- A modeling library with virtual components for SystemC and TLM simulators☆154Updated last week
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆165Updated 3 weeks ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆235Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆201Updated this week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆103Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆422Updated 2 weeks ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆96Updated 2 months ago
- BookSim 2.0☆325Updated 10 months ago
- An AXI4 crossbar implementation in SystemVerilog☆147Updated last week
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- RiVEC Bencmark Suite☆114Updated 5 months ago
- Comment on the rocket-chip source code☆179Updated 6 years ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆150Updated 2 years ago
- ☆84Updated this week
- Instruction Set Generator initially contributed by Futurewei☆279Updated last year
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆149Updated this week
- Fast and accurate DRAM power and energy estimation tool☆158Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆139Updated 3 months ago
- Wrapper for Rocket-Chip on FPGAs☆133Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆65Updated 10 months ago