tukl-msd / DRAMSysLinks
DRAMSys a SystemC TLM-2.0 based DRAM simulator.
☆316Updated last month
Alternatives and similar repositories for DRAMSys
Users that are interested in DRAMSys are comparing it to the libraries listed below
Sorting:
- A Chisel RTL generator for network-on-chip interconnects☆218Updated this week
- Network on Chip Simulator☆291Updated 2 weeks ago
- Modeling Architectural Platform☆212Updated this week
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆286Updated 2 weeks ago
- DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator☆418Updated last year
- BookSim 2.0☆380Updated last year
- An integrated power, area, and timing modeling framework for multicore and manycore architectures☆201Updated 5 years ago
- ☆204Updated 4 months ago
- Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model☆190Updated this week
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆251Updated 3 years ago
- SystemC/TLM-2.0 Co-simulation framework☆258Updated 5 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆155Updated 9 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆391Updated 3 weeks ago
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆469Updated 3 months ago
- A Fast, Low-Overhead On-chip Network☆232Updated 2 weeks ago
- RISC-V SystemC-TLM simulator☆329Updated this week
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆161Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆178Updated 2 months ago
- Vector processor for RISC-V vector ISA☆130Updated 5 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆143Updated this week
- GPGPU supporting RISCV-V, developed with verilog HDL☆122Updated 8 months ago
- ☆111Updated last week
- RiVEC Bencmark Suite☆123Updated 11 months ago
- ☆195Updated 2 weeks ago
- Network on Chip Implementation written in SytemVerilog☆193Updated 3 years ago
- Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and …☆431Updated 3 weeks ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆123Updated last week
- Lab exercises for Chisel in the digital electronics 2 course at DTU☆214Updated 5 months ago
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆35Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago