Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulatorLinks
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
☆55Updated 8 years ago
Alternatives and similar repositories for cycle-accurate-SystemC-simulator-over-ramulator
Users that are interested in cycle-accurate-SystemC-simulator-over-ramulator are comparing it to the libraries listed below
Sorting:
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆15Updated 11 years ago
- Project repo for the POSH on-chip network generator☆52Updated 8 months ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- Public release☆58Updated 6 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 2 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆71Updated 2 years ago
- An integrated CGRA design framework☆91Updated 8 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- gem5 repository to study chiplet-based systems☆84Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆31Updated 2 years ago
- Ratatoskr NoC Simulator☆28Updated 4 years ago
- ☆79Updated 11 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- ☆28Updated 6 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆45Updated 8 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago
- ☆24Updated 5 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆107Updated last year
- Example code for Modern SystemC using Modern C++☆68Updated 3 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆68Updated 4 months ago
- ☆32Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year