Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
☆48Updated 7 years ago
Alternatives and similar repositories for cycle-accurate-SystemC-simulator-over-ramulator:
Users that are interested in cycle-accurate-SystemC-simulator-over-ramulator are comparing it to the libraries listed below
- cycle accurate Network-on-Chip Simulator☆27Updated last year
- Project repo for the POSH on-chip network generator☆44Updated this week
- HLS for Networks-on-Chip☆33Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆56Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- SystemC training aimed at TLM.☆27Updated 4 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ☆26Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆41Updated 6 years ago
- ☆91Updated last year
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- ☆25Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- Public release☆50Updated 5 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆45Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆89Updated 5 months ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆24Updated this week