Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulatorLinks
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
☆50Updated 7 years ago
Alternatives and similar repositories for cycle-accurate-SystemC-simulator-over-ramulator
Users that are interested in cycle-accurate-SystemC-simulator-over-ramulator are comparing it to the libraries listed below
Sorting:
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆28Updated 4 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆32Updated 7 years ago
- Ratatoskr NoC Simulator☆26Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Project repo for the POSH on-chip network generator☆46Updated 2 months ago
- ☆91Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated last month
- ☆26Updated last year
- ☆49Updated 6 years ago
- ☆35Updated 4 years ago
- SystemC training aimed at TLM.☆29Updated 4 years ago
- ☆27Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆63Updated 5 years ago
- ☆30Updated 2 months ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆10Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- An integrated CGRA design framework☆88Updated 2 months ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- gem5 repository to study chiplet-based systems☆74Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated this week
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆48Updated 3 years ago
- Public release☆51Updated 5 years ago
- Advanced Architecture Labs with CVA6☆61Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆67Updated last year
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago