intel / systemc-compiler

Related projects: ⓘ

• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆353Updated this week
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆210Updated last week
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆212Updated 4 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆498Updated 2 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆284Updated this week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆191Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆418Updated last month
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆253Updated last week
• subbdue / systemverilog.io
  Code used in
  ☆168Updated 7 years ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆328Updated this week
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆281Updated 2 weeks ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆253Updated this week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆286Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆243Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆494Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆255Updated 11 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆199Updated 3 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆226Updated 2 weeks ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆127Updated this week
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆208Updated last month
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆192Updated this week
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆191Updated last year
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆218Updated 9 months ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆200Updated last week
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆480Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆225Updated this week
• accellera-official / systemc
  SystemC Reference Implementation
  ☆469Updated last month
• RoaLogic / RV12
  RISC-V CPU Core
  ☆280Updated 3 months ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆266Updated 4 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆280Updated 3 weeks ago