intel / systemc-compilerLinks
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
☆284Updated last week
Alternatives and similar repositories for systemc-compiler
Users that are interested in systemc-compiler are comparing it to the libraries listed below
Sorting:
- SystemC/TLM-2.0 Co-simulation framework☆256Updated 4 months ago
- SystemRDL 2.0 language compiler front-end☆261Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆416Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆233Updated last month
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆282Updated 2 weeks ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆217Updated 2 weeks ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆117Updated last week
- A modeling library with virtual components for SystemC and TLM simulators☆168Updated last week
- Code used in☆197Updated 8 years ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆384Updated 2 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆294Updated this week
- Build Customized FPGA Implementations for Vivado☆343Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆201Updated 11 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆232Updated 10 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆344Updated this week
- Official Hoi4 Hearts of Abexilas Repository☆11Updated last week
- RISC-V Virtual Prototype☆177Updated 9 months ago
- ☆189Updated last year
- RISC-V Verification Interface☆107Updated last week
- Verilog Configurable Cache☆183Updated 10 months ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆231Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆266Updated last week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆282Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆228Updated last week
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆305Updated 3 months ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆532Updated last month
- BaseJump STL: A Standard Template Library for SystemVerilog☆611Updated last week
- SystemVerilog synthesis tool☆211Updated 6 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆217Updated 3 weeks ago