Alternatives and similar repositories for systemc

Users that are interested in systemc are comparing it to the libraries listed below

• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆702Updated last month
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆575Updated last week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆626Updated this week
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆277Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆551Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆631Updated 2 weeks ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,077Updated last week
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,128Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆500Updated 3 months ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆490Updated 3 weeks ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,287Updated last week
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆311Updated 5 months ago
• riscv-non-isa / riscv-arch-test
  ☆564Updated 3 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆429Updated 8 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆393Updated last week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆494Updated 6 months ago
• Xilinx / HLS
  Vitis HLS LLVM source code and examples
  ☆389Updated 7 months ago
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆707Updated 2 weeks ago
• syntacore / scr1
  SCR1 is a high-quality open-source RISC-V MCU core in Verilog
  ☆915Updated 6 months ago
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆429Updated 2 weeks ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆284Updated last year
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆247Updated 2 weeks ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆373Updated 3 weeks ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆563Updated last month
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆879Updated 2 years ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,026Updated 3 years ago
• ucb-bar / berkeley-hardfloat
  ☆326Updated 8 months ago
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆757Updated this week
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆741Updated 9 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆426Updated 3 weeks ago