Alternatives and similar repositories for ESYSim

Users that are interested in ESYSim are comparing it to the libraries listed below

• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆52Updated 8 years ago
• hyoukjun / OpenSMART
  Public release
  ☆56Updated 6 years ago
• zhaishaomin / ring_network-based-multicore-
  多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency
  ☆26Updated 9 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆36Updated 4 years ago
• pulp-platform / fpu
  ☆53Updated 6 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆78Updated 10 years ago
• ucb-bar / uciedigital
  Pure digital components of a UCIe controller
  ☆69Updated last week
• ljgibbslf / basic_cache_core
  ☆29Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆67Updated 5 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆62Updated 3 weeks ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated last month
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆11Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆35Updated 6 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆41Updated last year
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆76Updated 7 years ago
• chsgcxy / messy_notes
  all kind of notes, I maybe sort this in the future
  ☆13Updated 3 weeks ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆18Updated 6 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆27Updated 4 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆54Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆80Updated 2 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆62Updated 3 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆32Updated 5 years ago
• tom-urkin / Round-Robin
  This repository contains a SystemVerilog implementation of a parametrized Round Robin arbiter with three instantiation options
  ☆12Updated last year