Alternatives and similar repositories for vcml

Users that are interested in vcml are comparing it to the libraries listed below

• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆256Updated 4 months ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆155Updated 4 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆117Updated last week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆177Updated 9 months ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆121Updated 2 years ago
• sparcians / map
  Modeling Architectural Platform
  ☆206Updated this week
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆93Updated 6 years ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆284Updated last week
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆107Updated last week
• chipsalliance / VeeR-ISS
  ☆145Updated 2 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated last month
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 3 months ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated 11 months ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last month
• quic / qbox
  Qbox
  ☆59Updated this week
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆325Updated 9 months ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆189Updated 3 weeks ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆306Updated 2 weeks ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆32Updated 5 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆66Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆232Updated 10 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆37Updated 3 years ago
• chipsalliance / uvm-verilator
  ☆97Updated 2 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated this week
• systemc / systemc-2.3
  New release of the systemc libraries
  ☆123Updated 13 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆75Updated 5 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆228Updated last week