Alternatives and similar repositories for vcml

Users that are interested in vcml are comparing it to the libraries listed below

• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆114Updated this week
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆255Updated 3 months ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆155Updated 3 months ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆177Updated 9 months ago
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆93Updated 6 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆320Updated 8 months ago
• sparcians / map
  Modeling Architectural Platform
  ☆202Updated 3 weeks ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆283Updated 3 weeks ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆120Updated 2 years ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆187Updated last week
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆302Updated 4 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 2 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆103Updated 3 months ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆61Updated 2 weeks ago
• chipsalliance / VeeR-ISS
  ☆145Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated 3 weeks ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆86Updated 11 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆281Updated 4 months ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 11 years ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• quic / qbox
  Qbox
  ☆58Updated 2 weeks ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆65Updated 2 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆93Updated 3 weeks ago
• subbdue / systemverilog.io
  Code used in
  ☆195Updated 8 years ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆44Updated 3 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆181Updated 9 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago