Alternatives and similar repositories for muchiSim

Users that are interested in muchiSim are comparing it to the libraries listed below

• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆86Updated 6 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆109Updated last year
• Yinxiao-Feng / chiplet-network-sim
  ☆54Updated 8 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆71Updated last month
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆62Updated 10 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• topanitanw / Cacti-7.0
  ☆24Updated 9 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆82Updated 4 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆85Updated 2 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆67Updated 4 years ago
• hngenc / stellar
  ☆32Updated last year
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆71Updated 4 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆47Updated 7 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆84Updated 4 years ago
• CMU-SAFARI / Sectored-DRAM
  A new DRAM substrate that mitigates the excessive energy consumption from both (i) transmitting unused data on the memory channel and (i…
  ☆13Updated last year
• arkhadem / aim_simulator
  A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0
  ☆54Updated 6 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆152Updated this week
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆31Updated 2 years ago
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆145Updated 7 months ago
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆46Updated 3 years ago
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆56Updated 4 years ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆86Updated 5 months ago
• UVA-LavaLab / PIMeval-PIMbench
  PIMeval simulator and PIMbench suite
  ☆44Updated 2 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 10 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆74Updated 3 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• FCAS-LAB / Chiplet-Gem5-SharedMemory
  ☆38Updated last year
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆72Updated 6 months ago