Alternatives and similar repositories for muchiSim

Users that are interested in muchiSim are comparing it to the libraries listed below

• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆121Updated 2 years ago
• GT-CHIPS / gem5_chips
  gem5 repository to study chiplet-based systems
  ☆77Updated 6 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆56Updated 4 months ago
• TeCSAR-UNCC / gem5-SALAM
  ☆92Updated last year
• Yinxiao-Feng / chiplet-network-sim
  ☆38Updated 2 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆60Updated 7 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆94Updated 10 months ago
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆135Updated last month
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆76Updated 6 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆82Updated last year
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆67Updated 3 months ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆85Updated 3 months ago
• tsinghua-ideal / spada-sim
  The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow
  ☆38Updated 2 years ago
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆55Updated 4 years ago
• topanitanw / Cacti-7.0
  ☆14Updated 3 months ago
• FCAS-LAB / Chiplet-Gem5-SharedMemory
  ☆31Updated last year
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆84Updated 2 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆72Updated 10 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆135Updated 5 months ago
• PolyArch / gem-forge-framework
  ☆25Updated last year
• hngenc / stellar
  ☆30Updated 8 months ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆64Updated 3 years ago
• arkhadem / aim_simulator
  A simulator for SK hynix AiM PIM architecture based on Ramulator 2.0
  ☆30Updated last week
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆33Updated last month
• tukl-msd / DRAMPower
  Fast and accurate DRAM power and energy estimation tool
  ☆168Updated this week
• HewlettPackard / mcpat
  An integrated power, area, and timing modeling framework for multicore and manycore architectures
  ☆190Updated 4 years ago
• UVA-LavaLab / PIMeval-PIMbench
  PIMeval simulator and PIMbench suite
  ☆32Updated this week
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆90Updated 4 months ago
• ConvolutedDog / HyFiSS
  HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
  ☆36Updated 7 months ago