PrincetonUniversity / muchiSim
Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore designs
☆47Updated 4 months ago
Related projects ⓘ
Alternatives and complementary repositories for muchiSim
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆64Updated 5 years ago
- gem5 repository to study chiplet-based systems☆67Updated 5 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated this week
- Heterogeneous simulator for DECADES Project☆29Updated 6 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- ☆84Updated 9 months ago
- CGRA Compilation Framework☆81Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆116Updated 4 years ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator☆51Updated 3 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- ☆37Updated 4 months ago
- A toolchain for rapid design space exploration of chiplet architectures☆33Updated 6 months ago
- ☆51Updated this week
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆30Updated 9 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- Release of stream-specialization software/hardware stack.☆116Updated last year
- EQueue Dialect☆39Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆74Updated last year
- ☆38Updated 8 months ago
- A list of our chiplet simulaters☆21Updated 3 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆49Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆38Updated 6 months ago
- A High-Level DRAM Timing, Power and Area Exploration Tool☆23Updated 4 years ago
- ☆57Updated last year
- ☆24Updated 5 months ago