ekiwi / fst-readerLinks
Native Rust implementation of the FST waveform format from GTKWave.
☆13Updated last week
Alternatives and similar repositories for fst-reader
Users that are interested in fst-reader are comparing it to the libraries listed below
Sorting:
- 21st century electronic design automation tools, written in Rust.☆30Updated last week
- Verilator Porcelain☆47Updated last year
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆70Updated this week
- Logic circuit analysis and optimization☆40Updated 8 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated last year
- Read and write VCD (Value Change Dump) files in Rust☆43Updated last year
- Fiber-based SystemVerilog Simulator.☆25Updated 2 years ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆28Updated 4 months ago
- Verilog AST☆21Updated last year
- A Hardware Pipeline Description Language☆44Updated last year
- Hardware generator debugger☆74Updated last year
- Bitstream Fault Analysis Tool☆14Updated last year
- A SystemVerilog source file pickler.☆57Updated 8 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆44Updated 5 months ago
- ☆40Updated 2 weeks ago
- System on Chip toolkit for Amaranth HDL☆91Updated 8 months ago
- PicoRV☆44Updated 5 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆33Updated last year
- Testing processors with Random Instruction Generation☆38Updated last week
- An automatic clock gating utility☆49Updated 2 months ago
- ☆56Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆35Updated 3 months ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆36Updated 4 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated last month
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated 3 weeks ago
- The LLHD reference simulator.☆39Updated 4 years ago
- ☆17Updated 3 months ago
- For contributions of Chisel IP to the chisel community.☆61Updated 7 months ago
- A configurable SRAM generator☆51Updated this week