Alternatives and similar repositories for fst-reader

Users that are interested in fst-reader are comparing it to the libraries listed below

• djg / verilated-rs
  Verilator Porcelain
  ☆49Updated last year
• ucb-substrate / substrate2
  21st century electronic design automation tools, written in Rust.
  ☆31Updated last week
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆97Updated 2 months ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆42Updated 2 months ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆44Updated last year
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• Kuree / fsim
  Fiber-based SystemVerilog Simulator.
  ☆25Updated 3 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆76Updated last year
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆53Updated last week
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated 3 weeks ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• lethalbit / discretize
  A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad
  ☆13Updated last year
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆34Updated last year
• fabianschuiki / llhd-sim
  The LLHD reference simulator.
  ☆39Updated 5 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆48Updated 10 months ago
• ethanuppal / marlin
  🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
  ☆69Updated last week
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆90Updated last month
• fabianschuiki / moore
  A hardware compiler based on LLHD and CIRCT
  ☆263Updated 4 months ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆65Updated last week
• abs-tudelft / Tydi-Chisel
  ☆18Updated last month
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 6 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 4 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago
• eschkufz / cascade
  A Just-In-Time Compiler for Verilog from VMware Research
  ☆22Updated 4 years ago
• stefanpie / sa-placer
  ☆16Updated last year
• antmicro / sv-bugpoint
  ☆30Updated 2 weeks ago
• inferablejump / bagpype
  ☆15Updated 2 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 5 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆37Updated 4 years ago