ekiwi / fst-readerLinks
Native Rust implementation of the FST waveform format from GTKWave.
☆13Updated last month
Alternatives and similar repositories for fst-reader
Users that are interested in fst-reader are comparing it to the libraries listed below
Sorting:
- Verilator Porcelain☆49Updated 2 years ago
- Logic circuit analysis and optimization☆45Updated 4 months ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆103Updated last week
- Read and write VCD (Value Change Dump) files in Rust☆44Updated last year
- 21st century electronic design automation tools, written in Rust.☆33Updated last week
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆49Updated 11 months ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- design and verification of asynchronous circuits☆41Updated last month
- Hardware generator debugger☆77Updated last year
- End-to-end synthesis and P&R toolchain☆92Updated 3 weeks ago
- A SystemVerilog language server based on the Slang library.☆91Updated this week
- ☆20Updated 3 months ago
- An automatic clock gating utility☆51Updated 8 months ago
- ☆15Updated 2 weeks ago
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆77Updated last week
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆13Updated last year
- An open-source custom cache generator.☆34Updated last year
- The LLHD reference simulator.☆39Updated 5 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated 3 weeks ago
- AXI Formal Verification IP☆21Updated 4 years ago
- Industry standard I/O for Amaranth HDL☆30Updated last year
- RISC-V out-of-order core for education and research purposes☆81Updated 2 weeks ago
- ☆33Updated last week
- ☆16Updated last year
- A Just-In-Time Compiler for Verilog from VMware Research☆23Updated 5 years ago
- ☆41Updated 2 weeks ago
- Mutation Cover with Yosys (MCY)☆89Updated 3 weeks ago