Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
☆52Jan 13, 2021Updated 5 years ago
Alternatives and similar repositories for svreal
Users that are interested in svreal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Automatic generation of real number models from analog circuits☆49Apr 2, 2024Updated 2 years ago
- A framework for FPGA emulation of mixed-signal systems☆39Jul 28, 2021Updated 5 years ago
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- Determines the modules declared and instantiated in a SystemVerilog file☆51Sep 23, 2024Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Open Source PHY v2☆36Apr 25, 2024Updated 2 years ago
- PLL Simulator in SystemC-AMS☆11Jun 2, 2023Updated 3 years ago
- Generated files from ANTLR4 for Verilog parsing in Python☆12Jul 12, 2022Updated 4 years ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- Debuggable hardware generator☆71Feb 17, 2023Updated 3 years ago
- ☆14Apr 29, 2024Updated 2 years ago
- A home for Genesis2 sources.☆47Jun 15, 2026Updated last month
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 3 weeks ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated last year
- Running Python code in SystemVerilog☆73May 8, 2026Updated 2 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆478Jun 10, 2026Updated last month
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- magma circuits☆264Oct 19, 2024Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- A git subcommand to apply skeleton repository continuously☆15Jul 20, 2026Updated last week
- ☆10Nov 2, 2023Updated 2 years ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆676Jul 7, 2026Updated 3 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A library and command-line tool for querying a Verilog netlist.☆30Jun 13, 2022Updated 4 years ago
- The UVM written in Python☆18Updated this week
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆90Apr 13, 2026Updated 3 months ago
- RISCV Core written in Calyx☆17Aug 16, 2024Updated last year
- Log file scanner used with EDA tools to classify errors and warnings☆13Nov 14, 2022Updated 3 years ago
- My local copy of UVM-SystemC☆14Apr 27, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆35Oct 15, 2024Updated last year
- High quality and composable RTL libraries in SystemVerilog☆44Updated this week
- Fork of gem5 with support for manycore architectures. Includes models and scripts to evaluate a software-defined-vector architecture.☆13Oct 14, 2021Updated 4 years ago
- Toolbox for working with the Python AST☆16Sep 13, 2023Updated 2 years ago
- Python library for accessing elevation data☆24Sep 23, 2024Updated last year
- Python package for IBIS-AMI model development and testing☆36Updated this week
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 10 years ago