Alternatives and similar repositories for svreal

Users that are interested in svreal are comparing it to the libraries listed below

• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 2 months ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆43Updated last year
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆59Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆35Updated 2 weeks ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆38Updated 2 months ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆23Updated 4 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆96Updated last month
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆62Updated 7 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆50Updated 5 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆78Updated 4 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆53Updated last year
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆28Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated 11 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 7 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆29Updated 2 years ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆80Updated 10 months ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated 2 weeks ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆37Updated 2 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated 2 weeks ago
• vsdip / vsdsram_sky130
  ☆42Updated 3 years ago