SystemVerilog grammar for tree-sitter
☆113Nov 11, 2024Updated last year
Alternatives and similar repositories for tree-sitter-verilog
Users that are interested in tree-sitter-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog tree-sitter grammar☆47Feb 23, 2026Updated last month
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆468Nov 4, 2025Updated 4 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆369Updated this week
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- SystemVerilog compiler and language services☆989Mar 22, 2026Updated last week
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆105Jun 27, 2022Updated 3 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 9 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil …☆454Mar 8, 2026Updated 3 weeks ago
- SystemVerilog linter☆379Nov 6, 2025Updated 4 months ago
- Python script to transform a VCD file to wavedrom format☆84Aug 18, 2022Updated 3 years ago
- tree-sitter grammar/parser for INI files☆31Dec 8, 2025Updated 3 months ago
- A VHDL parser for syntax highlighting.☆21Mar 15, 2026Updated 2 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,797Mar 13, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- PCBNEW plugin that highlights pads on a PCB that meet specified criteria (part, unit, number, name, and function).☆25Sep 17, 2021Updated 4 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- A Verilog Synthesis Regression Test☆37Jan 19, 2026Updated 2 months ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆54Jul 22, 2021Updated 4 years ago
- A Verilog parser for Haskell.☆36Jul 6, 2021Updated 4 years ago
- SystemVerilog language server☆567Mar 18, 2026Updated last week
- An abstraction library for interfacing EDA tools☆756Updated this week
- Extended and external tests for Verilator testing☆17Mar 11, 2026Updated 2 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 4 months ago
- mantle library☆44Dec 20, 2022Updated 3 years ago
- A VHDL frontend for Yosys☆104Feb 27, 2017Updated 9 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆142Mar 16, 2026Updated 2 weeks ago
- ☆13Mar 18, 2026Updated last week
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Apr 18, 2022Updated 3 years ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- datasheet generator☆30Jul 18, 2025Updated 8 months ago
- VHDL grammar for tree-sitter☆32Dec 20, 2023Updated 2 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated last year
- The ZipCPU blog☆18Dec 17, 2025Updated 3 months ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆23Oct 24, 2023Updated 2 years ago
- MLIR grammar for tree-sitter☆19Mar 15, 2026Updated 2 weeks ago
- A hardware compiler based on LLHD and CIRCT☆266Jun 30, 2025Updated 9 months ago