cuhk-eda / cu-gr-2Links
☆48Updated last year
Alternatives and similar repositories for cu-gr-2
Users that are interested in cu-gr-2 are comparing it to the libraries listed below
Sorting:
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆149Updated 6 months ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆54Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆141Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆135Updated last year
- ☆35Updated 5 years ago
- ☆39Updated 4 years ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆85Updated last year
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆140Updated 2 years ago
- The first version of TritonPart☆31Updated last year
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆60Updated 6 months ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆30Updated 3 years ago
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆24Updated last year
- ISPD26 Contest: Post-Placement Buffering and Sizing☆21Updated last week
- ☆20Updated 11 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆109Updated last year
- GPU-based logic synthesis tool☆97Updated last month
- VLSI EDA Global Router☆79Updated 7 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆60Updated 11 months ago
- Artificial Netlist Generator☆46Updated last year
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆189Updated 7 months ago
- ☆60Updated 4 years ago
- ☆10Updated 8 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆39Updated last week
- This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.☆34Updated 2 years ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆75Updated 6 months ago
- ☆90Updated 6 months ago
- Encoder-decoder based generative networks for static and transient thermal analysis☆23Updated 2 years ago
- BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…☆21Updated 7 years ago
- Mirror of the Si2 LEF/DEF parser (v5.8)☆17Updated 4 years ago
- NTHU CS6135 VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing Floorplan Design…☆42Updated 3 months ago