cuhk-eda / cu-gr-2Links
☆44Updated last year
Alternatives and similar repositories for cu-gr-2
Users that are interested in cu-gr-2 are comparing it to the libraries listed below
Sorting:
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆42Updated 7 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆136Updated 2 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆127Updated last week
- ☆30Updated 4 years ago
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆29Updated 3 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆126Updated 11 months ago
- Artificial Netlist Generator☆39Updated last year
- ☆13Updated 11 months ago
- The first version of TritonPart☆27Updated last year
- GPU-based logic synthesis tool☆81Updated this week
- ☆20Updated 5 months ago
- ☆10Updated 2 months ago
- Mirror of the Si2 LEF/DEF parser (v5.8)☆15Updated 3 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆45Updated last week
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆135Updated 2 years ago
- ☆12Updated last year
- the awesome work, project and lab of EDA (Electronic Design Automation). continue update...☆23Updated 9 months ago
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆76Updated 10 months ago
- VLSI EDA Global Router☆73Updated 7 years ago
- Timing prediction dataset download and instructions.☆15Updated 2 years ago
- Bounded-Skew DME v1.3☆14Updated 6 years ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆30Updated 2 weeks ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆56Updated 4 years ago
- GPU-Accelerated Global Router☆18Updated 7 months ago
- ☆17Updated 9 months ago
- ☆9Updated 3 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆56Updated 4 years ago
- UCSD Detailed Router☆88Updated 4 years ago
- ☆33Updated 4 years ago