[NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs
☆16Feb 22, 2026Updated 6 months ago
Alternatives and similar repositories for ArithTreeRL
Users that are interested in ArithTreeRL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆20Oct 26, 2025Updated 10 months ago
- A Lean-embedded framework to verify Verilog modules☆15Aug 15, 2026Updated 2 weeks ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Aug 25, 2021Updated 5 years ago
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆30Oct 28, 2024Updated last year
- GPU-based logic synthesis tool☆110Mar 31, 2026Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Jan 14, 2025Updated last year
- ☆18Feb 25, 2026Updated 6 months ago
- ☆25Jun 23, 2024Updated 2 years ago
- Initial version of CircuitGCL☆16Aug 19, 2025Updated last year
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 4 months ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆20Jan 17, 2026Updated 7 months ago
- [ICML 2023] ChiPFormer: Transferable Chip Placement via Offline Decision Transformer☆57Feb 22, 2026Updated 6 months ago
- Yosys RTLIL dialect for MLIR☆24Jun 12, 2025Updated last year
- Hardcaml Verification Tools☆20Jul 10, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- [NeurIPS 2022 Spotlight] MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning☆72Jan 5, 2026Updated 7 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆152Jul 23, 2025Updated last year
- Connecting bv_decide to SMTLIB.☆16Updated this week
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- AI-Assisted Verification of Data Structures☆22May 27, 2026Updated 3 months ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆14Aug 26, 2024Updated 2 years ago
- Using e-graphs for logic synthesis (ICCAD'25)☆37Updated this week
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆24Jan 28, 2026Updated 7 months ago
- This is the code for our paper "Reinforcement Learning within Tree Search for Fast Macro Placement".☆39Nov 13, 2024Updated last year
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- A Python library for working with logic networks, synthesis, and optimization.☆88Updated this week
- ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms☆74Sep 22, 2025Updated 11 months ago
- ☆19Jul 2, 2024Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆59Jan 8, 2025Updated last year
- ☆20Jan 2, 2026Updated 8 months ago
- [AAAI 2025 Oral] AnalogCoder: Analog Circuit Design via Training-Free Code Generation☆194Feb 22, 2026Updated 6 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An experimental package manager and development tool for Hardware Description Languages (HDL).☆14Apr 10, 2022Updated 4 years ago
- Official code for DeepGate4☆15Jun 25, 2026Updated 2 months ago
- Python version of tools to work with AIG formatted files☆13May 20, 2025Updated last year
- The first large scale formally verified reasoning dataset for Verilog☆24May 16, 2025Updated last year
- Official Implementation of "Circuit Transformer: A Transformer That Preserves Logical Equivalence"☆28Mar 13, 2025Updated last year
- Official implementation of MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy (ASP-DAC 2023)☆18Jun 3, 2023Updated 3 years ago
- A tool for cross-checking Verilog compilers☆15Apr 16, 2025Updated last year