esa-tu-darmstadt / tapasco
The Task Parallel System Composer (TaPaSCo)
☆106Updated 3 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for tapasco
- ☆87Updated 8 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- Examples for creating AXI-interfaced peripherals in Chisel☆71Updated 9 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆62Updated 5 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆57Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆117Updated last year
- Next generation CGRA generator☆106Updated this week
- An open source high level synthesis (HLS) tool built on top of LLVM☆118Updated 5 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆64Updated 2 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆121Updated last year
- high-performance RTL simulator☆140Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.☆135Updated last year
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆103Updated 4 months ago
- ☆66Updated last year
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆145Updated last week
- ☆75Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 3 months ago
- A dynamic verification library for Chisel.☆142Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week