esa-tu-darmstadt / tapascoLinks
The Task Parallel System Composer (TaPaSCo)
☆111Updated 2 months ago
Alternatives and similar repositories for tapasco
Users that are interested in tapasco are comparing it to the libraries listed below
Sorting:
- Next generation CGRA generator☆113Updated last week
- An open source high level synthesis (HLS) tool built on top of LLVM☆124Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆162Updated 2 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- high-performance RTL simulator☆170Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- ☆87Updated last year
- A dynamic verification library for Chisel.☆154Updated 9 months ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆113Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆83Updated 10 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆103Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆178Updated 3 months ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆71Updated 11 months ago
- ☆103Updated 3 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆62Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆166Updated last year
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated 2 weeks ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated 3 weeks ago
- Chisel components for FPGA projects☆126Updated last year
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆110Updated this week
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆277Updated 3 months ago