esa-tu-darmstadt / tapasco
The Task Parallel System Composer (TaPaSCo)
☆108Updated this week
Alternatives and similar repositories for tapasco
Users that are interested in tapasco are comparing it to the libraries listed below
Sorting:
- Next generation CGRA generator☆111Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated last month
- ☆86Updated last year
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆102Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆121Updated 11 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated last year
- ☆93Updated last year
- A dynamic verification library for Chisel.☆150Updated 6 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 7 months ago
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆155Updated 3 weeks ago
- CVA6 SDK containing RISC-V tools and Buildroot☆66Updated 10 months ago
- ☆81Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆54Updated 3 years ago
- A Fast, Low-Overhead On-chip Network☆203Updated this week
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 8 months ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆104Updated last week
- Tile based architecture designed for computing efficiency, scalability and generality☆253Updated this week
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 3 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated last week
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆164Updated last year
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last week