accellera-official / crave
Constrained RAndom Verification Enviroment (CRAVE)
☆17Updated last year
Alternatives and similar repositories for crave:
Users that are interested in crave are comparing it to the libraries listed below
- Python/Simulator integration using procedure calls☆9Updated 5 years ago
- Common SystemVerilog RTL modules for RgGen☆12Updated last month
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- Useful UVM extensions☆21Updated 8 months ago
- SystemVerilog Linter based on pyslang☆29Updated 2 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 10 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- ☆14Updated 3 weeks ago
- UVM Python Verification Agents Library☆14Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- Platform Level Interrupt Controller☆36Updated 10 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated 2 weeks ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆23Updated 2 weeks ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 2 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 8 months ago
- hardware library for hwt (= ipcore repo)☆37Updated 3 months ago
- Import and export IP-XACT XML register models☆33Updated 4 months ago
- Cross EDA Abstraction and Automation☆36Updated 2 weeks ago
- Open source RTL simulation acceleration on commodity hardware☆24Updated last year
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- APB UVC ported to Verilator☆11Updated last year
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Python Tool for UVM Testbench Generation☆50Updated 9 months ago
- Python interface for cross-calling with HDL☆31Updated this week
- ☆31Updated last year
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 4 months ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆23Updated 4 years ago