accellera-official / crave

Related projects ⓘ

Alternatives and complementary repositories for crave

• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆31Updated 7 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆20Updated 4 months ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆15Updated last week
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆25Updated 3 weeks ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆15Updated 6 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆23Updated 8 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆22Updated last month
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆34Updated 5 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated last month
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆13Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆33Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆48Updated 6 months ago
• avidan-efody / wave_searcher
  Implementation of post-process coverage, and batch waveform search
  ☆15Updated 3 years ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆36Updated 12 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆23Updated last week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆34Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆47Updated 2 months ago
• chipsalliance / UHDM-integration-tests
  ☆30Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆23Updated last week
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆32Updated 9 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆38Updated 5 months ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆21Updated 3 years ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆21Updated last month
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆25Updated 6 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆34Updated 8 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆53Updated 4 months ago