PrincetonUniversity / smappicLinks
☆22Updated 2 years ago
Alternatives and similar repositories for smappic
Users that are interested in smappic are comparing it to the libraries listed below
Sorting:
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆74Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆56Updated 8 years ago
- An integrated CGRA design framework☆91Updated 10 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- ☆32Updated last year
- An Open-Source Tool for CGRA Accelerators☆81Updated 4 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- Processing in Memory Emulation☆22Updated 2 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A fast, accurate trace-based simulator for High-Level Synthesis.☆74Updated last month
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 6 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆84Updated 4 years ago
- A toolchain for rapid design space exploration of chiplet architectures☆72Updated 6 months ago
- ☆24Updated 5 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Updated 6 years ago
- ☆55Updated 7 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated last week
- Public release☆58Updated 6 years ago
- ☆108Updated last year
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆70Updated 2 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆127Updated 3 years ago
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 6 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated 3 weeks ago
- HLS for Networks-on-Chip☆39Updated 4 years ago
- gem5 repository to study chiplet-based systems☆85Updated 6 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Updated last year
- CGRA framework with vectorization support.☆42Updated this week
- ☆62Updated 10 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 5 years ago