iree-org / iree-bare-metal-armLinks
Example for running IREE in a bare-metal Arm environment.
☆40Updated 6 months ago
Alternatives and similar repositories for iree-bare-metal-arm
Users that are interested in iree-bare-metal-arm are comparing it to the libraries listed below
Sorting:
- ☆36Updated this week
- HeteroCL-MLIR dialect for accelerator design☆42Updated last year
- IREE plugin repository for the AMD AIE accelerator☆119Updated last week
- Bridging polyhedral analysis tools to the MLIR framework☆119Updated 2 years ago
- ☆123Updated this week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆141Updated last week
- ☆90Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines (FPGA 2025 Best Paper Nominee)☆57Updated this week
- ☆38Updated last year
- Polyhedral High-Level Synthesis in MLIR☆35Updated 2 years ago
- Chisel RISC-V Vector 1.0 Implementation☆129Updated 4 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆53Updated 2 years ago
- LLVM OpenCL C compiler suite for ventus GPGPU☆58Updated last month
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Updated 7 months ago
- This project records the process of optimizing SGEMM (single-precision floating point General Matrix Multiplication) on the riscv platfor…☆24Updated last year
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆101Updated 7 months ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)☆44Updated 2 weeks ago
- A polyhedral compiler for hardware accelerators☆59Updated last year
- The Riallto Open Source Project from AMD☆84Updated 9 months ago
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆91Updated 3 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated 3 weeks ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆88Updated 2 years ago
- ☆62Updated last week
- Buda Compiler Backend for Tenstorrent devices☆30Updated 10 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- Fork of LLVM to support AMD AIEngine processors☆187Updated last week
- A Language for Closed-form High-level ARchitecture Modeling☆21Updated 5 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆46Updated 2 weeks ago