iree-org / iree-bare-metal-armLinks
Example for running IREE in a bare-metal Arm environment.
☆33Updated 3 months ago
Alternatives and similar repositories for iree-bare-metal-arm
Users that are interested in iree-bare-metal-arm are comparing it to the libraries listed below
Sorting:
- HeteroCL-MLIR dialect for accelerator design☆40Updated 8 months ago
- Bridging polyhedral analysis tools to the MLIR framework☆111Updated last year
- Polyhedral High-Level Synthesis in MLIR☆31Updated 2 years ago
- ☆99Updated this week
- ☆19Updated this week
- a simple end to end example of taking a ML graph (TF2 / PyTorch) and running it on a device [cpu, gpu]☆34Updated 4 years ago
- Xilinx Modifications to Halide☆13Updated 4 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 6 months ago
- ☆35Updated 10 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- Data-Centric MLIR dialect☆42Updated last year
- A stream to RTL compiler based on MLIR and CIRCT☆15Updated 2 years ago
- MLIRX is now defunct. Please see PolyBlocks - https://docs.polymagelabs.com☆38Updated last year
- Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC☆29Updated 2 months ago
- ☆29Updated 2 years ago
- ☆41Updated 2 weeks ago
- IREE plugin repository for the AMD AIE accelerator☆97Updated this week
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- EQueue Dialect☆40Updated 3 years ago
- An MLIR-based toy DL compiler for TVM Relay.☆58Updated 2 years ago
- A Language for Closed-form High-level ARchitecture Modeling☆20Updated 5 years ago
- A polyhedral compiler for hardware accelerators☆57Updated 10 months ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆22Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆40Updated 2 weeks ago
- Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)☆31Updated last year
- Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus☆27Updated 2 weeks ago
- Conversions to MLIR EmitC☆128Updated 5 months ago
- ☆61Updated this week
- 📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.☆14Updated 2 years ago