☆18Jan 15, 2026Updated last month
Alternatives and similar repositories for BSVTools
Users that are interested in BSVTools are comparing it to the libraries listed below
Sorting:
- SystemVerilog file list pruner☆17Mar 2, 2026Updated last week
- ☆11Jan 2, 2026Updated 2 months ago
- The Task Parallel System Composer (TaPaSCo)☆118Feb 6, 2026Updated last month
- Main page☆32Feb 12, 2020Updated 6 years ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆14Updated this week
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- OpenSoC Fabric - A Network-On-Chip Generator☆18Jun 12, 2017Updated 8 years ago
- Fast Symbolic Repair of Hardware Design Code☆33Jan 20, 2025Updated last year
- ☆26Jul 27, 2017Updated 8 years ago
- Interchange formats for chip design.☆37Feb 15, 2026Updated 3 weeks ago
- Sources of the Xyna Factory Server, Xyna runtime applications (like GuiHttp or gitintegration), and installation scripts.☆19Updated this week
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- ☆14May 24, 2025Updated 9 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- Isomorphic JavaScript helper functions (crpyto, performance, ..)☆11Jul 18, 2023Updated 2 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- 🚅🌎 Provide useful and comprehensive information for railway staff travel in Europe using FIP☆15Updated this week
- Convert REWE eBons (receipts) from PDF to JSON and CSV tables☆18Nov 22, 2025Updated 3 months ago
- Vim plugin for Bluespec SystemVerilog (BSV)☆11Nov 8, 2020Updated 5 years ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 8 months ago
- Example project for the BRS-100-GW1NR9 FPGA development board.☆14Feb 14, 2026Updated 3 weeks ago
- FDTD 3D simulator that generates s-parameters from OFF geometry files using one or more GPUs☆15Jan 16, 2023Updated 3 years ago
- Python implementation of a simple neural network, including AND, OR, and XOR demos.☆11Jun 13, 2019Updated 6 years ago
- ROACH2 hardware gerbers, layout and bom☆11May 31, 2013Updated 12 years ago
- repo for CIS 371 Spring 2018☆15Apr 14, 2018Updated 7 years ago
- A data acquisition framework in Python and Verilog.☆43Feb 27, 2026Updated last week
- R implementation of Contextual Importance and Utility for Explainable AI☆10Nov 5, 2025Updated 4 months ago
- The slow loris attack, now implemented in Rust!☆12May 9, 2022Updated 3 years ago
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 7 years ago
- Add support for debugging JITed code to ORC JIT from LLVM Kaleidoscope example☆13Jun 14, 2017Updated 8 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- The T-Shirt artwork of the JSConf EU performance.☆10Sep 27, 2015Updated 10 years ago
- A straightforward (complete) sample of how to implement AES-GCM by using Linux crypto API at kernel side☆12Oct 6, 2022Updated 3 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- ☆13May 17, 2018Updated 7 years ago
- A Z80 CPU implemented in Chisel.☆11Sep 20, 2020Updated 5 years ago
- Examples of using Diderot☆11Sep 16, 2019Updated 6 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 5 years ago
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated last year