OpenCAPI / OpenCAPI3.0_Client_RefDesign
An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
☆11Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for OpenCAPI3.0_Client_RefDesign
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 7 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆64Updated 2 months ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated 9 months ago
- Library of open source Process Design Kits (PDKs)☆28Updated last week
- Source-Opened RISCV for Crypto☆14Updated 2 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- ☆52Updated 2 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 5 years ago
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆12Updated 3 months ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆21Updated 4 years ago
- tools regarding on analog modeling, validation, and generation☆21Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆25Updated 4 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆33Updated 4 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆36Updated 2 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- ☆22Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- ☆39Updated 4 years ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆15Updated 6 months ago
- SoCRocket - Core Repository☆33Updated 7 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 9 years ago
- For contributions of Chisel IP to the chisel community.☆55Updated 2 weeks ago