Alternatives and similar repositories for OpenCAPI3.0_Client_RefDesign

Users that are interested in OpenCAPI3.0_Client_RefDesign are comparing it to the libraries listed below

• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 5 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆24Updated last year
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆68Updated 8 months ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated last week
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆16Updated 3 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated last week
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated last week
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆18Updated 7 years ago
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆25Updated 3 years ago
• joey1115 / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆12Updated 6 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated last year
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last week
• b224hisl / rioschip
  ☆33Updated 2 years ago