Alternatives and similar repositories for OpenCAPI3.0_Client_RefDesign:

Users that are interested in OpenCAPI3.0_Client_RefDesign are comparing it to the libraries listed below

• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• opencomputeproject / ODSA-BoW
  Repo for all activity related to the ODSA Bunch of Wires Specification
  ☆24Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• SeanZarzycki / openSPARC-FPU
  ASIC Design of the openSPARC Floating Point Unit
  ☆13Updated 8 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated 2 weeks ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 4 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 2 months ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated 2 weeks ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆68Updated 7 months ago
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆15Updated 3 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆46Updated 4 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated 2 weeks ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆51Updated 3 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• zhemao / riscv-dma3
  The 3rd Iteration of the Berkeley RISC-V DMA Accelerator
  ☆27Updated 5 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆64Updated last month
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆25Updated 3 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last month
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago