OpenCAPI / OpenCAPI3.0_Client_RefDesign
An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
☆13Updated 2 years ago
Alternatives and similar repositories for OpenCAPI3.0_Client_RefDesign:
Users that are interested in OpenCAPI3.0_Client_RefDesign are comparing it to the libraries listed below
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 11 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated this week
- AXI X-Bar☆19Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 7 months ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆17Updated 11 months ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- A basic documentation generator for Verilog, similar to Doxygen.☆11Updated 8 years ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- The source code that empowers OpenROAD Cloud☆12Updated 4 years ago
- ☆22Updated 8 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆17Updated 8 months ago
- Xilinx Unisim Library in Verilog☆75Updated 4 years ago
- Source-Opened RISCV for Crypto☆15Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- ☆27Updated 2 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- ☆18Updated 4 years ago
- Extended and external tests for Verilator testing☆16Updated last week