OpenCAPI / OpenCAPI3.0_Client_RefDesignLinks
An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
☆14Updated 2 years ago
Alternatives and similar repositories for OpenCAPI3.0_Client_RefDesign
Users that are interested in OpenCAPI3.0_Client_RefDesign are comparing it to the libraries listed below
Sorting:
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- ☆66Updated 2 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆23Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆71Updated last year
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- ☆56Updated 3 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 months ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Source-Opened RISCV for Crypto☆16Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Open Source PHY v2☆29Updated last year
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆37Updated 3 months ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- ☆44Updated 5 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆39Updated 2 years ago
- A library of verilog and vhdl modules☆15Updated 6 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A home for Genesis2 sources.☆42Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Advanced Debug Interface☆15Updated 7 months ago