OpenCAPI / OpenCAPI3.0_Client_RefDesignLinks
An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development
☆15Updated 3 years ago
Alternatives and similar repositories for OpenCAPI3.0_Client_RefDesign
Users that are interested in OpenCAPI3.0_Client_RefDesign are comparing it to the libraries listed below
Sorting:
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 7 months ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- ☆44Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆55Updated 3 years ago
- Open Source PHY v2☆33Updated last year
- Source-Opened RISCV for Crypto☆18Updated 4 years ago
- ☆68Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- FPU Generator☆20Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- ASIC Design of the openSPARC Floating Point Unit☆15Updated 8 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Repo for all activity related to the ODSA Bunch of Wires Specification☆29Updated 2 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Open source process design kit for 28nm open process☆72Updated last year
- ☆38Updated 3 years ago
- SoCRocket - Core Repository☆38Updated 8 years ago
- APB UVC ported to Verilator☆11Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Updated last month
- Python interface to FPGA interchange format☆41Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 4 months ago