RISCV-on-Microsemi-FPGA / CPUsLinks
CPUs
☆14Updated 4 years ago
Alternatives and similar repositories for CPUs
Users that are interested in CPUs are comparing it to the libraries listed below
Sorting:
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- The home of the Chisel3 website☆21Updated last year
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆21Updated 4 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- APB UVC ported to Verilator☆11Updated last year
- Open Source PHY v2☆31Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Basic Common Modules☆44Updated 2 months ago
- ☆40Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 2 weeks ago
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆121Updated last week
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- ☆50Updated last month
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆49Updated 4 years ago
- FOS - FPGA Operating System☆73Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆67Updated 11 months ago
- ☆33Updated 5 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆50Updated 9 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Doxygen with verilog support☆39Updated 6 years ago
- RISC-V Virtual Prototype☆44Updated 4 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆53Updated last year
- PCI Express controller model☆68Updated 3 years ago
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago