RISCV-on-Microsemi-FPGA / CPUs
CPUs
☆14Updated 4 years ago
Alternatives and similar repositories for CPUs:
Users that are interested in CPUs are comparing it to the libraries listed below
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated last week
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆40Updated 3 months ago
- Extensible FPGA control platform☆59Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- ☆59Updated 3 years ago
- Spen's Official OpenOCD Mirror☆48Updated 2 weeks ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- ☆29Updated 7 years ago
- Basic Common Modules☆37Updated 3 months ago
- Advanced Debug Interface☆14Updated 2 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Demo SoC for SiliconCompiler.☆57Updated 3 weeks ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- ☆33Updated 2 years ago
- ☆21Updated 2 months ago
- ☆27Updated 3 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- ☆21Updated 7 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆83Updated last week
- ☆36Updated 2 years ago
- An open-source custom cache generator.☆33Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 8 months ago
- ☆36Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 3 months ago
- VHDL PCIe Transceiver☆28Updated 4 years ago