Alternatives and similar repositories for UHDM-integration-tests:

Users that are interested in UHDM-integration-tests are comparing it to the libraries listed below

• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆68Updated last week
• pulp-platform / svase
  ☆31Updated last week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆53Updated 2 months ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 6 months ago
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆26Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 4 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated 2 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 4 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆25Updated last week
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆25Updated last week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆29Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated 3 months ago
• aolofsson / POSH
  ☆40Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆48Updated 2 weeks ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆55Updated 3 months ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 5 months ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆34Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆56Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 10 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 3 weeks ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆63Updated last month
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆24Updated 3 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆78Updated last month
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago