jiegec / cpu

Related projects ⓘ

Alternatives and complementary repositories for cpu

• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆10Updated 7 months ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated last year
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆21Updated last year
• JohndeVostok / APE
  A GPU FP32 computation method with Tensor Cores.
  ☆18Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆55Updated 2 years ago
• were / bfsh
  Being a full-stack hacker, RISCV, LLVM, and more.
  ☆18Updated 3 years ago
• jiegec / kb
  My knowledge base
  ☆39Updated this week
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated 7 months ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆28Updated last week
• dramforever / ixayoi
  (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
  ☆12Updated 3 years ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆13Updated 4 years ago
• CircuitCoder / mill
  RV32I by cats
  ☆17Updated last year
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆17Updated 3 weeks ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆25Updated this week
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 2 years ago
• gty111 / PTX-EMU
  PTX-EMU is a simple emulator for CUDA program.
  ☆24Updated 10 months ago
• sifive / riscv-vector-intrinsic-fuzzing
  A random fuzz generator for the RISC-V vector extension intrinsics
  ☆18Updated 3 weeks ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆27Updated this week
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 2 years ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆11Updated 2 weeks ago
• efeslab / moesi-prime
  ☆14Updated last year
• trivialmips / TrivialMIPS_Software
  Baremetal softwares for TrivialMIPS platform
  ☆10Updated 5 years ago
• TrivialCompiler / Talk
  Tex source for talk slide.
  ☆10Updated 3 years ago
• heterosys / mlir-vitis
  📥 🎯 (1,4/4) an MLIR-based toolchain with Vitis HLS LLVM input/output targeting FPGAs.
  ☆13Updated 2 years ago
• OpenRigil / openrigil-rtl
  Open-source RISC-V cryptographic hardware token, RTL repo
  ☆19Updated 2 years ago
• yhtzd / skyloft
  Skyloft: A General High-Efficient Scheduling Framework in User Space (SOSP 2024)
  ☆22Updated 2 months ago
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆11Updated last week