Alternatives and similar repositories for MicroArchBench

Users that are interested in MicroArchBench are comparing it to the libraries listed below

• OpenXiangShan / GEM5
  ☆123Updated this week
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆68Updated 2 years ago
• shinezyy / gem5_data_proc
  data preprocessing scripts for gem5 output
  ☆19Updated 8 months ago
• cry-daniel / Computer-Architecture-Learning
  ☆64Updated 3 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆44Updated 2 years ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆24Updated 8 months ago
• OpenXiangShan / XSAI
  A fork of Xiangshan for AI
  ☆36Updated last week
• OpenXiangShan / gsim
  ☆65Updated last month
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 4 years ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆33Updated last year
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆75Updated last week
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• xuefeng16 / Tyche-Artifact
  [TACO 2024] A hardware prefetching framework employing Tyche, a hardware prefetcher designed for indirect memory access patterns.
  ☆25Updated last year
• OSCPU / archbench
  ☆11Updated last month
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆51Updated last month
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆36Updated 3 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 4 months ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• dhschall / gem5-fdp
  Development repository for Fetch Directed Instruction Prefetching (FDP) in gem5
  ☆30Updated last week
• RoyanTuscano / -TAGE-based-Predictor-Verilog-Code
  Verilog Implementation of TAGE based predictor by Andre Seznec and Pierre Michaud
  ☆20Updated 7 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆193Updated last year
• SamAinsworth / gem5-triangel
  ☆22Updated 10 months ago
• HIT-MaRiver-mips / cpucore-mariver
  ☆35Updated 2 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆40Updated 2 years ago
• hpsresearchgroup / scarab
  Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator
  ☆83Updated 4 months ago
• pku-liang / ksim
  ☆52Updated last year
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆28Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆32Updated 9 months ago
• ysyx-ta / ysyx-summer-readings
  ☆66Updated last year
• lshpku / gem5-runahead
  Implementing the Precise Runahead (HPCA'20) in gem5
  ☆13Updated 2 years ago