Alternatives and similar repositories for verilogModuleAddPrefix

Users that are interested in verilogModuleAddPrefix are comparing it to the libraries listed below

• ysyx-ta / ysyx-summer-readings
  ☆66Updated 11 months ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆176Updated 9 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 3 months ago
• OSCPU / ysyxSoC
  ☆86Updated 3 months ago
• OSCPU / yosys-sta
  ☆74Updated 3 months ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆22Updated 5 months ago
• Jpz-sdju / trinity
  ☆24Updated last week
• puckbee / moli
  ☆27Updated last week
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 4 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 3 years ago
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆18Updated 7 months ago
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆18Updated 4 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• OSCPU / ysyx-workbench
  ☆156Updated this week
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 10 months ago
• OpenXiangShan / gsim
  ☆44Updated this week
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆29Updated 2 weeks ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆64Updated last year
• MaZirui2001 / Zircon
  ☆27Updated 6 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 9 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated last year
• OSCPU / openperf
  ☆11Updated 5 months ago
• OpenXiangShan / GEM5
  ☆93Updated this week
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆60Updated this week
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆81Updated last year
• fluctlight001 / Generic-Cache-Module
  适用于龙芯杯团队赛入门选手的应急cache模块
  ☆28Updated last year
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆23Updated 8 months ago