MrAMS / verilogModuleAddPrefix
verilog module add prefix script 可用于ysyx项目添加学号
☆13Updated 8 months ago
Related projects ⓘ
Alternatives and complementary repositories for verilogModuleAddPrefix
- "aura" my super-scalar O3 cpu core☆24Updated 5 months ago
- ☆76Updated 2 months ago
- ☆60Updated 3 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆116Updated last month
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆25Updated 7 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆16Updated 4 months ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆46Updated 2 years ago
- ☆43Updated 4 months ago
- ☆65Updated this week
- ☆119Updated 2 months ago
- A RISC-V RV32I ISA Single Cycle CPU☆20Updated last year
- 2022龙芯杯个人赛三等奖作品☆13Updated last year
- ☆62Updated 3 months ago
- Modern co-simulation framework for RISC-V CPUs☆118Updated this week
- A Study of the SiFive Inclusive L2 Cache☆45Updated 10 months ago
- Pick your favorite language to verify your chip.☆31Updated this week
- 2020龙芯杯个人赛 简易双发射60M(含ibuffer)☆34Updated 4 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆22Updated 8 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆43Updated 2 weeks ago
- ☆52Updated last year
- ☆56Updated 4 months ago
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆8Updated 7 months ago
- ☆63Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 8 months ago
- 一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .☆24Updated 2 years ago
- Basic chisel difftest environment for RTL design (WIP☆14Updated 3 months ago
- ☆32Updated last year
- 龙芯杯个人赛工具包(适用于个人赛的golden_trace工具)☆48Updated 8 months ago
- ☆31Updated last year
- A small SoC with a pipeline 32-bit RISC-V CPU.☆62Updated 2 years ago