Alternatives and similar repositories for Gemmini_doc

Users that are interested in Gemmini_doc are comparing it to the libraries listed below

• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆17Updated 6 months ago
• VCA-EPFL / FSA
  FSA: Fusing FlashAttention within a Single Systolic Array
  ☆51Updated last month
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• Jpz-sdju / trinity
  ☆28Updated 2 months ago
• OSCPU / yosys-sta
  ☆83Updated 5 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆58Updated 3 months ago
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆75Updated 6 months ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆43Updated 2 years ago
• OSCPU / ysyxSoC
  ☆87Updated this week
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆29Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 6 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆74Updated 3 weeks ago
• scalesim-project / scale-sim-v3
  ☆45Updated last month
• THU-DSP-LAB / ventus-gpgpu-verilog
  GPGPU supporting RISCV-V, developed with verilog HDL
  ☆113Updated 7 months ago
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆11Updated 4 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆59Updated 6 months ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆23Updated 9 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆66Updated this week
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆93Updated 5 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆70Updated 2 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• FPSG-UIUC / micro24-fusemax-artifact
  MICRO 2024 Evaluation Artifact for FuseMax
  ☆14Updated last year
• vickyiii / Quick-Start-Guide-for-HLS
  This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…
  ☆23Updated 2 years ago
• pulp-platform / ITA
  ☆49Updated 5 months ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆132Updated 4 months ago
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆34Updated 4 months ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆112Updated 5 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆70Updated last week
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago