Alternatives and similar repositories for efficient_checksum-offload-engine

Users that are interested in efficient_checksum-offload-engine are comparing it to the libraries listed below

• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 5 years ago
• alexforencich / dma-bench
  ☆27Updated 3 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆22Updated last year
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago
• lucasbrasilino / net2axis
  Verilog network module. Models network traffic from pcap to AXI-Stream
  ☆23Updated 4 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆66Updated 3 weeks ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• UCLA-VAST / HT-Deflate-FPGA
  ☆15Updated 3 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆54Updated 2 years ago
• tymonx / virtio
  Virtio implementation in SystemVerilog
  ☆47Updated 7 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 9 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆30Updated 9 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆22Updated last year
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated 11 months ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆49Updated 4 years ago
• pulp-platform / axi_llc
  ☆29Updated 3 weeks ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆63Updated 3 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated last week
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆19Updated last year
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆26Updated 3 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆111Updated 3 years ago
• chipsalliance / caliptra-ss
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
  ☆29Updated last week
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 7 months ago
• rsarwar87 / xdma_dsc_byp_cltr
  VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe
  ☆17Updated 5 years ago
• StanfordVLSI / FP-Gen
  FPU Generator
  ☆20Updated 4 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆29Updated last year
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆69Updated last week