Alternatives and similar repositories for efficient_checksum-offload-engine:

Users that are interested in efficient_checksum-offload-engine are comparing it to the libraries listed below

• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆43Updated last year
• luinaudt / deparser
  ☆16Updated 3 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆21Updated last year
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆22Updated 3 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆27Updated 2 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆60Updated 2 months ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 10 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• mcjtag / tcam
  TCAM (Ternary Content-Addressable Memory) in Verilog
  ☆43Updated last year
• chipsalliance / aib-protocols
  ☆25Updated 11 months ago
• oprecomp / DDR4_controller
  ☆50Updated 3 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆15Updated 5 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆41Updated 7 months ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆61Updated 2 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆43Updated 10 years ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆12Updated last month
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆101Updated 2 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆47Updated 2 years ago
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆18Updated last year
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆59Updated last year
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆26Updated last month
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆27Updated last month
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆44Updated 8 years ago