Alternatives and similar repositories for efficient_checksum-offload-engine:

Users that are interested in efficient_checksum-offload-engine are comparing it to the libraries listed below

• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• RSPwFPGAs / opae-xilinx
  OPAE porting to Xilinx FPGA devices.
  ☆39Updated 4 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆23Updated last year
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆44Updated last year
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆18Updated 6 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆102Updated 3 years ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• opensmartnic / cocotb_primer
  understanding of cocotb （In Chinese Only）
  ☆15Updated last year
• maswx / vu13p_corundum
  corundum work on vu13p
  ☆18Updated last year
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆21Updated 6 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• luinaudt / deparser
  ☆16Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆61Updated 4 months ago
• merledu / OpenTCAM
  An open-source Ternary Content Addressable Memory (TCAM) compiler.
  ☆25Updated 7 months ago
• AmeerAbdelhadi / Indirectly-Indexed-2D-Ternary-Content-Addressable-Memory-TCAM
  Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
  ☆23Updated 3 months ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆41Updated last year
• alexforencich / dma-bench
  ☆25Updated 2 years ago
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆21Updated 2 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆43Updated 10 years ago
• slaclab / axi-pcie-core
  ☆21Updated this week
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆29Updated last month
• Xilinx / pcie_qdma_ats_example
  ☆22Updated 3 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 6 years ago
• UCLA-VAST / HT-Deflate-FPGA
  ☆14Updated 2 years ago
• fpgasystems / davos
  Distributed Accelerator OS
  ☆61Updated 2 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆48Updated 2 years ago