☆20May 5, 2020Updated 6 years ago
Alternatives and similar repositories for hwd-ide
Users that are interested in hwd-ide are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 2 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- A tool for modeling FSMs by VHDL or Verilog☆14Updated this week
- A JSON library implemented in VHDL.☆85Feb 8, 2026Updated 4 months ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Language server based on ghdl☆103Jun 3, 2026Updated last week
- An abstract language model of VHDL written in Python.☆64May 11, 2026Updated last month
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Mar 12, 2026Updated 3 months ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆52Jun 8, 2026Updated last week
- Building and deploying container images for open source electronic design automation (EDA)☆122Oct 3, 2024Updated last year
- VHDL grammar for tree-sitter☆32Dec 20, 2023Updated 2 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 3 years ago
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 7 months ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Streaming based VHDL parser.☆86Jul 15, 2024Updated last year
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- VHDL related news.☆27Updated this week
- D3.js based wave (signal) visualizer☆68Updated this week
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Feb 24, 2026Updated 3 months ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 4 years ago
- Sketches for DesignLab☆16Sep 10, 2017Updated 8 years ago
- VHDL code generator for AXI4-lite register files☆12May 22, 2024Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.☆85Feb 8, 2020Updated 6 years ago
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- Simple Python parser for extracting HDL (VHDL or Verilog) documentation☆24Mar 1, 2024Updated 2 years ago
- ☆16Nov 30, 2025Updated 6 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 4 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆43Mar 7, 2024Updated 2 years ago
- Sata 2 Host Controller for FPGA implementation☆18Oct 11, 2017Updated 8 years ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- ☆33Jun 2, 2026Updated last week
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆69Feb 16, 2026Updated 3 months ago