verilator / verilator_ext_testsLinks
Extended and external tests for Verilator testing
☆17Updated 3 weeks ago
Alternatives and similar repositories for verilator_ext_tests
Users that are interested in verilator_ext_tests are comparing it to the libraries listed below
Sorting:
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 8 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Cross EDA Abstraction and Automation☆40Updated 2 weeks ago
- SystemVerilog Linter based on pyslang☆31Updated 6 months ago
- Import and export IP-XACT XML register models☆36Updated 3 weeks ago
- A header only C++11 library for functional coverage☆36Updated 3 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆18Updated last year
- ☆20Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- UART models for cocotb☆32Updated 2 months ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Updated last year
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- Main repo for Go2UVM source code, examples and apps☆21Updated 2 years ago
- Various low power labs using sky130☆13Updated 4 years ago
- ☆19Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆63Updated last month
- ☆21Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated this week
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- ☆31Updated 2 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated last year
- Generate symbols from HDL components/modules☆21Updated 2 years ago