Extended and external tests for Verilator testing
☆19Oct 16, 2026Updated 2 weeks ago
Alternatives and similar repositories for verilator_ext_tests
Users that are interested in verilator_ext_tests are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆48Oct 6, 2026Updated 3 weeks ago
- RTLMeter benchmark suite☆34Updated this week
- AMIQ Externally Controlled Test Bench☆12Jan 13, 2025Updated last year
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆43Jun 24, 2026Updated 4 months ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆41Jan 23, 2024Updated 2 years ago
- Basic VCD comparison tool, for Verilator testing☆24Feb 24, 2026Updated 8 months ago
- Tool for graphically viewing FPGA bitstream files and their connection to FASM features.☆19Apr 6, 2022Updated 4 years ago
- Neovim frontend for enhanced features of the Slang SV language server☆16Oct 12, 2026Updated 2 weeks ago
- ☆30Oct 2, 2023Updated 3 years ago
- Announcements related to Verilator☆46Nov 2, 2025Updated 11 months ago
- A composite GitHub action for running busted tests with Neovim☆21Jan 21, 2026Updated 9 months ago
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 8 months ago
- AXI X-Bar☆19Apr 8, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilator open-source SystemVerilog simulator and lint system☆28Updated this week
- Verilog netlist parser/database (derived from http://nldb.sourceforge.net)☆13Dec 12, 2014Updated 11 years ago
- OpenPiton Design Benchmark☆30Mar 6, 2023Updated 3 years ago
- A python script that converts between schematic file formats☆21Dec 15, 2011Updated 14 years ago
- ☆20Aug 20, 2025Updated last year
- Simulation VCD waveform viewer, using old Motif UI☆28Apr 8, 2023Updated 3 years ago
- C++ library for dynamic graph layout☆11Jun 21, 2025Updated last year
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- Tiny framework for solving constraint satisfaction problems (CSP) with discrete and finite domains. This is a Scala-based port of the ori…☆11May 13, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Unofficial specification for GtkWave's FST digital waveform file format.☆11Jan 23, 2026Updated 9 months ago
- A suite of tools for pretty printing, diffing, and exploring abstract syntax trees.☆18Aug 11, 2026Updated 2 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆405Updated this week
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆18Aug 1, 2019Updated 7 years ago
- Unsupervised Learning : Q - Learning Algorithm on Arduino Uno☆10Nov 15, 2017Updated 8 years ago
- XC2064 bitstream documentation☆19Sep 24, 2018Updated 8 years ago
- ☆142Aug 14, 2026Updated 2 months ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Mar 6, 2022Updated 4 years ago
- Random ideas and interesting ideas for things we hope to eventually do.☆86Apr 4, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- A padring generator for ASICs☆27May 17, 2023Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆85May 14, 2024Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆149Jul 22, 2021Updated 5 years ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- ☆14Aug 24, 2026Updated 2 months ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 6 years ago