Alternatives and similar repositories for verilator_ext_tests:

Users that are interested in verilator_ext_tests are comparing it to the libraries listed below

• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago
• chipsalliance / tools-cocotb-verilator-build
  ☆13Updated 5 years ago
• Anushar123 / vsdsram
  SRAM
  ☆8Updated 4 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
  9 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆16Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last month
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 10 months ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆19Updated 3 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 4 years ago
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆25Updated 3 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 4 months ago
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆15Updated 3 years ago
• efabless / caravel-lite
  ☆15Updated 4 months ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆29Updated 10 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• vsdip / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆15Updated 4 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆35Updated 10 years ago
• The-OpenROAD-Project / OpenROAD-Cloud
  The source code that empowers OpenROAD Cloud
  ☆12Updated 4 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆31Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated this week
• b224hisl / rioschip
  ☆33Updated 2 years ago