Alternatives and similar repositories for verilator_ext_tests

Users that are interested in verilator_ext_tests are comparing it to the libraries listed below

• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆37Updated 3 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆13Updated 10 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 3 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆43Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆41Updated 2 months ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 4 months ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆19Updated last year
• wallento / cocotbext-uart
  UART cocotb module
  ☆11Updated 4 years ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 5 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆19Updated last year
• ieee-ceda-datc / datc-rdf-calibrations
  ☆19Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 4 years ago
• Minres / RDL-Editor
  A Xtext based SystemRDL editor with syntax highlighting and context sensitive help
  ☆12Updated 2 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆21Updated 2 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆33Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 9 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆33Updated 5 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆44Updated 3 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 3 months ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆13Updated 4 years ago
• efabless / caravel-lite
  ☆17Updated last year
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated last year
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆29Updated last year