Alternatives and similar repositories for SystemC-Engine

Users that are interested in SystemC-Engine are comparing it to the libraries listed below

• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 5 years ago
• Risto97 / systemc_uvm_verilator
  ☆12Updated 2 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 2 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆25Updated 2 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆13Updated last year
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆24Updated 3 months ago
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆23Updated 2 weeks ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆38Updated last week
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆25Updated 6 months ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆17Updated 2 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 10 months ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆32Updated 7 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆24Updated 4 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 7 months ago
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆45Updated last year
• amiq-consulting / amiq_ofc
  Open-Source Framework for Co-Emulation
  ☆12Updated 4 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆9Updated 2 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆27Updated 2 years ago
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆20Updated 6 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 7 months ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated this week
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated last month
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last month
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆39Updated 2 years ago