Alternatives and similar repositories for SystemC-Engine

Users that are interested in SystemC-Engine are comparing it to the libraries listed below

• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆30Updated last year
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆26Updated 3 years ago
• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 6 years ago
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆14Updated last year
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆21Updated last year
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆41Updated 2 months ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆18Updated 7 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• HEP-SoC / SoCMake
  CMake based hardware build system
  ☆35Updated last week
• Stuart-Swan / Matchlib-Examples-Kit-For-Accellera-Synthesis-WG
  ☆12Updated last week
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated last year
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆13Updated 9 years ago
• amiq-consulting / amiq_ofc
  Open-Source Framework for Co-Emulation
  ☆13Updated 4 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 9 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 2 months ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated 2 weeks ago
• TILhub / AMBA-3-AHB-Lite-Protocol
  This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
  ☆13Updated 7 years ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆20Updated 10 months ago
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆34Updated 2 months ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆18Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆48Updated last month