antmicro / tuttest
A simple Python utility for extracting documentation snippets from tutorials.
☆14Updated last year
Alternatives and similar repositories for tuttest:
Users that are interested in tuttest are comparing it to the libraries listed below
- HDL tools layer for OpenEmbedded☆17Updated 4 months ago
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- Virtual development board for HDL design☆40Updated last year
- A sphinx extension that allows including wavedrom diagrams by using its text-based representation☆35Updated 5 months ago
- cocotb extension for nMigen☆16Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆36Updated 2 months ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆13Updated 4 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆28Updated 5 months ago
- ☆39Updated last year
- Sphinx Extension which generates various types of diagrams from Verilog code.☆57Updated last year
- Generate symbols from HDL components/modules☆20Updated 2 years ago
- ☆31Updated last year
- Web-based HDL diagramming tool☆79Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A Sphinx domain providing VHDL language support.☆20Updated last year
- System on Chip toolkit for Amaranth HDL☆86Updated 4 months ago
- Cross EDA Abstraction and Automation☆36Updated this week
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆40Updated 9 months ago
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- IP-XACT XML binding library☆15Updated 8 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆110Updated 4 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated 2 weeks ago
- RFCs for changes to the Amaranth language and standard components☆18Updated 5 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- ☆35Updated 5 months ago
- GUI editor for hardware description designs☆27Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆51Updated last year