chiggs / oc_jpegencode
Fork of OpenCores jpegencode with Cocotb testbench
☆43Updated 9 years ago
Alternatives and similar repositories for oc_jpegencode:
Users that are interested in oc_jpegencode are comparing it to the libraries listed below
- Extensible FPGA control platform☆57Updated last year
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Wishbone interconnect utilities☆38Updated 3 weeks ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆34Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆78Updated 5 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 4 years ago
- ☆32Updated last year
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- UART models for cocotb☆26Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- ☆26Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Open source FPGA-based NIC and platform for in-network compute☆61Updated 4 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆62Updated 8 years ago
- Hamming ECC Encoder and Decoder to protect memories☆29Updated last month
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- JESD204b modules in VHDL☆29Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 5 months ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆33Updated 10 months ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 5 years ago
- Adding PR to the PYNQ Overlay☆17Updated 7 years ago