chiggs / oc_jpegencodeLinks
Fork of OpenCores jpegencode with Cocotb testbench
☆46Updated 10 years ago
Alternatives and similar repositories for oc_jpegencode
Users that are interested in oc_jpegencode are comparing it to the libraries listed below
Sorting:
- Extensible FPGA control platform☆61Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- ☆26Updated 2 years ago
- ☆33Updated 2 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- Advanced Debug Interface☆14Updated 9 months ago
- Small footprint and configurable JESD204B core☆49Updated 3 weeks ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Python interface to PCIE☆40Updated 7 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Verilog wishbone components☆121Updated last year
- ☆27Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆21Updated 9 years ago
- Verilog FT245 to AXI stream interface☆29Updated 7 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Wishbone interconnect utilities☆43Updated 9 months ago
- A tool for merging the MyHDL workflow with Vivado☆20Updated 5 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago