chiggs / oc_jpegencodeLinks
Fork of OpenCores jpegencode with Cocotb testbench
☆46Updated 9 years ago
Alternatives and similar repositories for oc_jpegencode
Users that are interested in oc_jpegencode are comparing it to the libraries listed below
Sorting:
- Extensible FPGA control platform☆62Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- ☆32Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- ☆26Updated 2 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Python interface to PCIE☆40Updated 7 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Small footprint and configurable JESD204B core☆45Updated 2 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- ☆22Updated 9 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆28Updated 9 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆38Updated 4 years ago
- Generic Logic Interfacing Project☆46Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated 3 weeks ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 6 months ago
- Reusable image processing modules in SystemVerilog☆34Updated 8 years ago
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Xilinx Unisim Library in Verilog☆84Updated 5 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated last week
- ☆27Updated 4 years ago