chiggs / oc_jpegencodeLinks
Fork of OpenCores jpegencode with Cocotb testbench
☆47Updated 10 years ago
Alternatives and similar repositories for oc_jpegencode
Users that are interested in oc_jpegencode are comparing it to the libraries listed below
Sorting:
- Extensible FPGA control platform☆61Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- ☆33Updated 2 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Updated 8 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆60Updated 2 months ago
- Small footprint and configurable JESD204B core☆45Updated 4 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- ☆26Updated 2 years ago
- Xilinx Unisim Library in Verilog☆85Updated 5 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆65Updated last week
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Verilog FT245 to AXI stream interface☆29Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 10 months ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- VHDL PCIe Transceiver☆30Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆67Updated 3 weeks ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- ☆21Updated 9 years ago
- UART models for cocotb☆30Updated 3 weeks ago