chiggs / oc_jpegencode

Related projects ⓘ

Alternatives and complementary repositories for oc_jpegencode

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 6 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆39Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆16Updated 5 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆29Updated 3 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆15Updated 4 years ago
• suoto / fpga_cores
  ☆32Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 6 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated 11 months ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆41Updated 2 years ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆43Updated 11 months ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆58Updated 3 weeks ago
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 4 years ago
• sjaeckel / axi-bfm
  git clone of http://code.google.com/p/axi-bfm/
  ☆17Updated 11 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆19Updated 4 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated last month
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆12Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆39Updated 6 years ago
• pulp-platform / axi_spi_slave
  ☆23Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 4 months ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago