chiggs / oc_jpegencodeLinks
Fork of OpenCores jpegencode with Cocotb testbench
☆45Updated 10 years ago
Alternatives and similar repositories for oc_jpegencode
Users that are interested in oc_jpegencode are comparing it to the libraries listed below
Sorting:
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- ☆26Updated 2 years ago
- ☆33Updated 2 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆37Updated 6 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆53Updated 2 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- ☆21Updated 9 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Updated 5 years ago
- Advanced Debug Interface☆14Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated last month
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated last year
- This repository contains synthesizable examples which use the PoC-Library.☆39Updated 5 years ago
- Python interface to PCIE☆40Updated 7 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Updated 8 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated last year
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Main repo for Go2UVM source code, examples and apps☆21Updated 2 years ago
- Reusable image processing modules in SystemVerilog☆34Updated 8 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆19Updated 8 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 13 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year