Alternatives and similar repositories for rudder:

Users that are interested in rudder are comparing it to the libraries listed below

• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated 10 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated last week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated 10 months ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• dbhi / vboard
  Virtual development board for HDL design
  ☆40Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆15Updated 3 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆22Updated 2 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• snishizawa / libretto
  Characterizer
  ☆21Updated 6 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆17Updated 4 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated 11 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆44Updated 7 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆44Updated last year
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆52Updated this week
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 3 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated 2 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 7 months ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆21Updated last year