Alternatives and similar repositories for rudder:

Users that are interested in rudder are comparing it to the libraries listed below

• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated 8 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆24Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆36Updated this week
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated last year
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆41Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆20Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 4 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated 2 weeks ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆73Updated 2 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆43Updated last year
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆22Updated last month
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 6 months ago
• dovebutch / tlv-comp
  ☆26Updated 3 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 4 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated last year
• dbhi / vboard
  Virtual development board for HDL design
  ☆40Updated last year
• phthinh / soric_project
  Source-Opened RISCV for Crypto
  ☆15Updated 3 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆29Updated 3 months ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated 10 months ago
• OSVVM / OSVVM-Scripts
  OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation
  ☆11Updated 3 weeks ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 6 months ago
• pezy-computing / flgen
  Filelist generator
  ☆15Updated last week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago