0x01be / rudderLinks
Learn, share and collaborate on ASIC design using open tools and technologies
☆13Updated 4 years ago
Alternatives and similar repositories for rudder
Users that are interested in rudder are comparing it to the libraries listed below
Sorting:
- Cross EDA Abstraction and Automation☆40Updated 2 weeks ago
- Virtual development board for HDL design☆42Updated 2 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆25Updated 4 months ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 3 months ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆12Updated 2 weeks ago
- ☆18Updated last year
- IP-XACT XML binding library☆16Updated 9 years ago
- Web-based HDL diagramming tool☆81Updated 2 years ago
- ☆20Updated 3 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆17Updated 2 years ago
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- hardware library for hwt (= ipcore repo)☆43Updated 3 weeks ago
- Characterizer☆30Updated 2 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆17Updated 3 years ago
- KLayout technology files for ASAP7 FinFET educational process☆22Updated 2 years ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 7 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Updated 6 years ago
- ☆31Updated 2 years ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆61Updated 2 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆66Updated last week
- ☆44Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- A padring generator for ASICs☆25Updated 2 years ago
- A framework for FPGA emulation of mixed-signal systems☆37Updated 4 years ago
- SystemVerilog Linter based on pyslang☆31Updated 6 months ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Generate symbols from HDL components/modules☆21Updated 2 years ago