wsong83 / cppVCD
cpp parser for reading a VCD (value change dump) file
☆10Updated 11 years ago
Alternatives and similar repositories for cppVCD:
Users that are interested in cppVCD are comparing it to the libraries listed below
- A basic documentation generator for Verilog, similar to Doxygen.☆11Updated 8 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Updated last year
- Cross EDA Abstraction and Automation☆36Updated this week
- A basic VCD parser☆7Updated 8 years ago
- ☆13Updated 9 months ago
- Parsing library for BLIF netlists☆18Updated 5 months ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- CMake based hardware build system☆16Updated this week
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Extended and external tests for Verilator testing☆16Updated this week
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Updated 6 years ago
- ☆18Updated 5 months ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆22Updated this week
- IP-XACT XML binding library☆15Updated 8 years ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆10Updated 6 years ago
- VCD (Value Change Dump) Tracing for C++☆9Updated 2 years ago
- ☆31Updated last year
- Open Source Detailed Placement engine☆11Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆14Updated 5 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆11Updated 10 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 3 months ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- ☆34Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Updated last year
- EDA physical synthesis optimization kit☆51Updated last year
- Mirror of tachyon-da cvc Verilog simulator☆42Updated last year
- DATC Robust Design Flow.☆37Updated 5 years ago