Alternatives and similar repositories for Surelog

Users that are interested in Surelog are comparing it to the libraries listed below

• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated last month
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆33Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆70Updated 9 months ago
• antmicro / verilator-verification-features-tests
  ☆23Updated this week
• alainmarcel / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆17Updated last week
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆28Updated 2 years ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated 2 weeks ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆40Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆69Updated 2 weeks ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆59Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆59Updated 5 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆49Updated 2 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆67Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 8 months ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated this week
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated 11 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆27Updated last year
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆61Updated 3 years ago
• pieter3d / simview
  ☆79Updated last year
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆51Updated 2 weeks ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 4 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 11 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago