alainmarcel / SurelogLinks
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆26Updated this week
Alternatives and similar repositories for Surelog
Users that are interested in Surelog are comparing it to the libraries listed below
Sorting:
- ☆31Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆72Updated 10 months ago
- SystemVerilog Linter based on pyslang☆31Updated 2 months ago
- Making cocotb testbenches that bit easier☆33Updated 2 weeks ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- SystemVerilog frontend for Yosys☆135Updated last week
- ☆79Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆67Updated 2 weeks ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago
- An automatic clock gating utility☆50Updated 3 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆17Updated this week
- ☆27Updated this week
- Running Python code in SystemVerilog☆70Updated last month
- A command-line tool for displaying vcd waveforms.☆59Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 5 months ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated last week
- Python library for operations with VCD and other digital wave files☆51Updated last month
- Python bindings for slang, a library for compiling SystemVerilog☆60Updated 5 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- A flexible framework for analyzing and transforming FPGA netlists. Official repository.☆95Updated 5 months ago
- hardware library for hwt (= ipcore repo)☆40Updated this week
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- Python interface for cross-calling with HDL☆34Updated last month
- A SystemVerilog source file pickler.☆59Updated 8 months ago
- SpinalHDL Hardware Math Library☆88Updated last year
- Generate address space documentation HTML from compiled SystemRDL input☆54Updated 3 weeks ago
- Simple parser for extracting VHDL documentation☆71Updated last year
- ☆26Updated last year
- Re-coded Xilinx primitives for Verilator use☆50Updated 3 weeks ago