SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆26May 31, 2026Updated last week
Alternatives and similar repositories for Surelog
Users that are interested in Surelog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆463May 31, 2026Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆258May 31, 2026Updated last week
- Python bindings for slang, a library for compiling SystemVerilog☆67Jan 18, 2025Updated last year
- ☆31Oct 2, 2023Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆35Apr 13, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog compiler and language services☆1,068Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆18May 31, 2026Updated last week
- This is the Verilog 2005 parser used by VerilogCreator☆15May 19, 2019Updated 7 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 7 months ago
- tools and techniques for building fast portable thread packages☆12Jul 10, 2013Updated 12 years ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated last year
- A Python package for creating and solving constrained randomization problems.☆19Oct 14, 2024Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 10 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆475Updated this week
- Performance Counters for Apple Silicon on macOS☆20Jan 9, 2022Updated 4 years ago
- SILVER - Statistical Independence and Leakage Verification☆17Jun 6, 2025Updated last year
- ☆43May 26, 2018Updated 8 years ago
- Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.☆13Nov 15, 2021Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆84May 14, 2024Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- A C version of Branch Predictor Simulator☆17Jul 10, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆98May 20, 2026Updated 3 weeks ago
- SystemVerilog synthesis tool☆234Mar 10, 2025Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆146May 14, 2026Updated 3 weeks ago
- A Language for Closed-form High-level ARchitecture Modeling☆21Feb 10, 2020Updated 6 years ago
- New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi…☆107Aug 28, 2025Updated 9 months ago
- Example of how to use UVM with Verilator☆45Apr 20, 2026Updated last month
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆15Feb 22, 2019Updated 7 years ago
- SystemVerilog linter☆384Nov 6, 2025Updated 7 months ago
- ☆29Jan 18, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆328Jun 30, 2025Updated 11 months ago
- ☆10Dec 29, 2023Updated 2 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆34Mar 7, 2026Updated 3 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆67Aug 18, 2021Updated 4 years ago
- Translation of the `Managing projects with GNU make' book to Russian.☆12May 26, 2013Updated 13 years ago
- Demonstrating systemverilog, verilator and google test for verification☆10Mar 3, 2021Updated 5 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 3 years ago