Alternatives and similar repositories for Surelog:

Users that are interested in Surelog are comparing it to the libraries listed below

• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆103Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated this week
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 3 months ago
• alainmarcel / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆17Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated 3 weeks ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆68Updated 9 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 6 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 9 months ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆29Updated last month
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆51Updated 2 weeks ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆49Updated 11 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• pulp-platform / svase
  ☆31Updated 4 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated last month
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated last week
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• antmicro / verilator-verification-features-tests
  ☆20Updated this week
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆59Updated 2 weeks ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆24Updated 2 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆76Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆41Updated last year
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆38Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago