alainmarcel / SurelogLinks
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆26Updated last week
Alternatives and similar repositories for Surelog
Users that are interested in Surelog are comparing it to the libraries listed below
Sorting:
- SystemVerilog Linter based on pyslang☆31Updated 3 months ago
- Making cocotb testbenches that bit easier☆34Updated 3 weeks ago
- SystemVerilog frontend for Yosys☆148Updated last week
- ☆79Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆73Updated 3 weeks ago
- An automatic clock gating utility☆50Updated 3 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆56Updated last month
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆71Updated 3 weeks ago
- Running Python code in SystemVerilog☆70Updated 2 months ago
- Python packages providing a library for Verification Stimulus and Coverage☆126Updated 3 weeks ago
- Python interface for cross-calling with HDL☆34Updated this week
- Python bindings for slang, a library for compiling SystemVerilog☆62Updated 6 months ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 6 months ago
- SpiceBind – spice inside HDL simulator☆48Updated last month
- Simple parser for extracting VHDL documentation☆71Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆63Updated this week
- ideas and eda software for vlsi design☆50Updated last week
- ☆31Updated last year
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- Python library for operations with VCD and other digital wave files☆51Updated 2 months ago
- Python script to transform a VCD file to wavedrom format☆78Updated 2 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Doxygen with verilog support☆38Updated 6 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆17Updated 2 weeks ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆55Updated last month
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Open Source Verification Bundle for VHDL and System Verilog☆45Updated last year
- A command-line tool for displaying vcd waveforms.☆59Updated last year