alainmarcel / Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
☆26Updated 2 months ago
Alternatives and similar repositories for Surelog:
Users that are interested in Surelog are comparing it to the libraries listed below
- SystemVerilog frontend for Yosys☆74Updated this week
- ☆31Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 5 months ago
- Doxygen with verilog support☆37Updated 5 years ago
- SystemVerilog Linter based on pyslang☆29Updated last month
- ☆17Updated this week
- Running Python code in SystemVerilog☆67Updated 7 months ago
- Making cocotb testbenches that bit easier☆27Updated last month
- ☆36Updated 2 years ago
- Python interface for cross-calling with HDL☆30Updated this week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆55Updated 2 months ago
- Open source RTL simulation acceleration on commodity hardware☆23Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆55Updated last month
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆17Updated 4 months ago
- ☆77Updated 11 months ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- ☆26Updated last year
- A command-line tool for displaying vcd waveforms.☆51Updated last year
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- Python library for operations with VCD and other digital wave files☆47Updated 8 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆35Updated 3 weeks ago
- Generate address space documentation HTML from compiled SystemRDL input☆48Updated 5 months ago
- An automatic clock gating utility☆43Updated 7 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆52Updated 4 months ago
- ☆31Updated last month
- Open Source Verification Bundle for VHDL and System Verilog☆43Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆29Updated 3 weeks ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆41Updated 11 months ago
- SystemVerilog FSM generator☆27Updated 9 months ago