Alternatives and similar repositories for EE219-AICS-2024

Users that are interested in EE219-AICS-2024 are comparing it to the libraries listed below

• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• Heresyrac / Gemmini_doc
  关于移植模型至gemmini的文档
  ☆27Updated 3 years ago
• BaoBao-zhu / RV-SCNN
  A Custom RISC-V Instruction Extension for SNN and CNN Computation
  ☆15Updated 9 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• kelvin0207 / SparSynergy
  Open source RTL implementation of Tensor Core, Sparse Tensor Core, BitWave and SparSynergy in the article: "SparSynergy: Unlocking Flexib…
  ☆16Updated 2 months ago
• hngenc / stellar
  ☆29Updated 6 months ago
• Jpz-sdju / trinity
  ☆21Updated 2 months ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• sfu-arch / SPAGHETTI
  RTL generator for SpGEMM
  ☆12Updated 4 years ago
• ConvolutedDog / gpgpu-sim-comments
  GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。
  ☆16Updated 5 months ago
• yizishun / ysyx-framework
  A framework for ysyx flow
  ☆11Updated 7 months ago
• loongson-community / open-la500
  Mirror of https://gitee.com/loongson-edu/open-la500.git
  ☆17Updated 5 months ago
• OSCPU / ysyxSoC
  ☆86Updated last month
• alexmr09 / Mixed-precision-Neural-Networks-on-RISC-V-Cores
  ☆28Updated last week
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆24Updated 2 years ago
• Davxx / gem5_Garnet2.0_extensions
  Fork of the gem5 simulator with Garnet2.0 and DSENT extensions
  ☆10Updated 6 years ago
• OSCPU / yosys-sta
  ☆64Updated last month
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆55Updated 3 years ago
• chenhaoc / ESL_Learning
  some knowleage about SystemC/TLM etc.
  ☆24Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 9 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆32Updated 2 months ago
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated last month
• Yinxiao-Feng / chiplet-network-sim
  ☆32Updated 5 months ago
• Rzfly / simple_riscv_soft_core
  This is a simple Risc-v core for software simulation on FPGA.
  ☆8Updated 3 years ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 8 months ago
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆24Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆33Updated 6 years ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆27Updated 2 weeks ago