LCAI-TIHU / HWLinks
LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.
☆41Updated 2 years ago
Alternatives and similar repositories for HW
Users that are interested in HW are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆53Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- ☆29Updated 4 years ago
- ☆34Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated last week
- ☆51Updated 6 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- ☆47Updated 2 months ago
- ☆61Updated 4 years ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- BlackParrot on Zynq☆43Updated 4 months ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- HLS for Networks-on-Chip☆35Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- ☆56Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆34Updated last year
- Simple single-port AXI memory interface☆42Updated last year
- Implementation of the PCIe physical layer☆44Updated 2 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- ☆26Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- Chisel implementation of Neural Processing Unit for System on the Chip☆21Updated 2 months ago