LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.
☆46Jan 6, 2023Updated 3 years ago
Alternatives and similar repositories for HW
Users that are interested in HW are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Dec 14, 2022Updated 3 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Jun 25, 2020Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆108Jan 27, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Qingnang Smart Diagnosis is an end-to-end AI healthcare framework with field-proven application capabilities, designed to provide efficie…☆27Jul 21, 2026Updated 2 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆22Sep 30, 2026Updated last week
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆19Oct 2, 2026Updated last week
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆56Jan 19, 2021Updated 5 years ago
- FPGA Low latency 10GBASE-R PCS☆13May 23, 2023Updated 3 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆107Jun 24, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Verilog Ethernet Switch (layer 2)☆60Oct 18, 2023Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- ☆37Oct 5, 2026Updated last week
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆20Jan 29, 2026Updated 8 months ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 12 years ago
- ☆26Oct 8, 2019Updated 7 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆70Mar 15, 2022Updated 4 years ago
- RTL modbus rtu slave for FPGA☆14Apr 29, 2022Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆187Dec 14, 2019Updated 6 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆45Mar 30, 2021Updated 5 years ago
- ☆20Jul 6, 2023Updated 3 years ago
- Userspace I/O library for Xilinx AXI S2MM DMA☆12Sep 9, 2025Updated last year
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆42Sep 30, 2026Updated last week
- ☆42Jun 9, 2022Updated 4 years ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆240Dec 22, 2025Updated 9 months ago
- ☆15Jul 28, 2022Updated 4 years ago
- ☆20Jun 10, 2026Updated 4 months ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆24May 20, 2026Updated 4 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- High-performance eBPF implementation in hardware.☆27Apr 5, 2022Updated 4 years ago
- Python script for controlling the debug-jtag port of riscv cores☆16Mar 27, 2021Updated 5 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 3 years ago
- ☆16Dec 4, 2021Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆124Nov 26, 2025Updated 10 months ago
- An Open-Source Design and Verification Environment for RISC-V☆90Apr 21, 2021Updated 5 years ago
- Matrix Multiplication in Hardware☆17Jun 3, 2020Updated 6 years ago