LCAI-TIHU / HW
LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.
☆37Updated 2 years ago
Alternatives and similar repositories for HW:
Users that are interested in HW are comparing it to the libraries listed below
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last month
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- ☆32Updated 6 years ago
- SoC Based on ARM Cortex-M3☆30Updated this week
- ☆27Updated 4 years ago
- ☆46Updated 6 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆19Updated 2 years ago
- ☆55Updated 4 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆29Updated this week
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆11Updated 2 years ago
- ☆51Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 6 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- ☆26Updated 5 years ago
- CNN accelerator using NoC architecture☆16Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago