LCAI-TIHU / HWLinks
LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peripherals.
☆42Updated 2 years ago
Alternatives and similar repositories for HW
Users that are interested in HW are comparing it to the libraries listed below
Sorting:
- ☆62Updated 3 years ago
- ☆35Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- ☆29Updated 5 years ago
- ☆53Updated 6 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆78Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆65Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆64Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated 11 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- Simple single-port AXI memory interface☆46Updated last year
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆15Updated 5 months ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- ☆66Updated 6 years ago
- round robin arbiter☆75Updated 11 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆27Updated 5 years ago