RuokaiYin / LoAS
LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.
☆10Updated last month
Alternatives and similar repositories for LoAS:
Users that are interested in LoAS are comparing it to the libraries listed below
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆10Updated last month
- ☆16Updated 11 months ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆26Updated 6 months ago
- The official implementation of HPCA 2025 paper, Prosperity: Accelerating Spiking Neural Networks via Product Sparsity☆24Updated 2 months ago
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆17Updated 11 months ago
- ☆12Updated last year
- NeuroSync: A Scalable and Accurate Brain Simulation System using Safe and Efficient Speculation (HPCA 2022)☆10Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 3 years ago
- ☆17Updated 4 years ago
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆18Updated last year
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆12Updated last year
- ☆17Updated 4 years ago
- I will share some useful or interesting papers about neuromorphic processor☆24Updated 2 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆14Updated 9 months ago
- ☆18Updated 2 years ago
- Open-source of MSD framework☆16Updated last year
- ☆26Updated 2 weeks ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆48Updated 3 weeks ago
- Framework for radix encoded SNN on FPGA☆12Updated 3 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆26Updated last year
- Spiking Neural Network Accelerator☆15Updated 2 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆12Updated 2 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆11Updated last year
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆51Updated 2 months ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆13Updated 7 months ago
- HW accelerator mapping optimization framework for in-memory computing☆22Updated 3 months ago
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated 9 months ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- ☆43Updated 3 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 2 years ago