Alternatives and similar repositories for Nitro-Parts-lib-Xilinx

Users that are interested in Nitro-Parts-lib-Xilinx are comparing it to the libraries listed below

• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆85Updated 5 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• fbrosser / DSP48E1-FP
  Project aimed at implementing floating point operators using the DSP48E1 slice.
  ☆29Updated 12 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆16Updated 5 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆42Updated 5 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆18Updated 8 years ago
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆29Updated 6 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 7 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated last year
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 8 months ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 6 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated 2 weeks ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 10 months ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 8 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆36Updated last month