dirjud / Nitro-Parts-lib-XilinxView external linksLinks
This is mainly a simulation library of xilinx primitives that are verilator compatible.
☆34Jul 15, 2024Updated last year
Alternatives and similar repositories for Nitro-Parts-lib-Xilinx
Users that are interested in Nitro-Parts-lib-Xilinx are comparing it to the libraries listed below
Sorting:
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 7 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Sep 2, 2023Updated 2 years ago
- ☆10Dec 18, 2017Updated 8 years ago
- Xilinx Unisim Library in Verilog☆86Jul 22, 2020Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- Open Processor Architecture☆26Apr 7, 2016Updated 9 years ago
- Small Stack-Based Computer Compiler -- Verilog micro controller for FPGA housekeeping with peripherals☆16Jan 11, 2020Updated 6 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 5 years ago
- JTAG Hardware Abstraction Library☆37Oct 23, 2023Updated 2 years ago
- Provides Spatial with front-end support from popular machine learning frameworks☆34Sep 30, 2019Updated 6 years ago
- Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!☆25Oct 19, 2016Updated 9 years ago
- XC2064 bitstream documentation☆18Sep 24, 2018Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- ☆19Oct 28, 2024Updated last year
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 7 years ago
- Files and documentation for Pico-Dirty-Blaster Workshop☆20Jun 21, 2025Updated 7 months ago
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- Prefix tree adder space exploration library☆56Jan 27, 2026Updated 2 weeks ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆134Updated this week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Jan 13, 2023Updated 3 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Bluespec SystemVerilog library for use of the IBM Coherent Accelerator-Processor Interface (CAPI)☆11May 25, 2016Updated 9 years ago
- Source code to accompany https://timetoexplore.net☆64Aug 25, 2020Updated 5 years ago
- understanding the tinyfpga bootloader☆25Apr 22, 2018Updated 7 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Jun 28, 2025Updated 7 months ago
- Chisel components for FPGA projects☆128Sep 19, 2023Updated 2 years ago
- ☆16Aug 21, 2019Updated 6 years ago
- FPGA Guide☆14Jan 2, 2022Updated 4 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- FPGA code for NeTV2☆15Dec 3, 2018Updated 7 years ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 12 years ago
- A vhdl package for reading and writing bitmap files.☆11Jan 9, 2018Updated 8 years ago
- TLUT tool flow for parameterised configurations for FPGAs☆16Aug 5, 2024Updated last year
- Build Customized FPGA Implementations for Vivado☆355Updated this week
- ☆25Sep 27, 2018Updated 7 years ago