dirjud / Nitro-Parts-lib-Xilinx
This is mainly a simulation library of xilinx primitives that are verilator compatible.
☆31Updated 4 months ago
Related projects ⓘ
Alternatives and complementary repositories for Nitro-Parts-lib-Xilinx
- Xilinx Unisim Library in Verilog☆71Updated 4 years ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆26Updated 6 years ago
- ☆36Updated 2 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆17Updated 7 years ago
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆14Updated 5 years ago
- A padring generator for ASICs☆22Updated last year
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Docker Development Environment for SpinalHDL☆18Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- Open source RTL simulation acceleration on commodity hardware☆22Updated last year
- JTAG DPI module for OpenRISC simulation with Verilator☆16Updated 12 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated 11 months ago
- Open Processor Architecture☆26Updated 8 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- Advanced Debug Interface☆12Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆26Updated 9 years ago
- ☆14Updated 4 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆30Updated 3 years ago
- ☆33Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- Generic Logic Interfacing Project☆44Updated 4 years ago