dirjud / Nitro-Parts-lib-XilinxLinks
This is mainly a simulation library of xilinx primitives that are verilator compatible.
☆34Updated last year
Alternatives and similar repositories for Nitro-Parts-lib-Xilinx
Users that are interested in Nitro-Parts-lib-Xilinx are comparing it to the libraries listed below
Sorting:
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Updated 12 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆18Updated 8 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆18Updated 6 years ago
- ☆38Updated 3 years ago
- ☆33Updated 3 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 6 months ago
- SoftCPU/SoC engine-V☆55Updated 9 months ago
- Advanced Debug Interface☆14Updated 11 months ago
- USB virtual model in C++ for Verilog☆32Updated last year
- Docker Development Environment for SpinalHDL☆20Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆30Updated 7 years ago
- ☆26Updated 5 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 13 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Updated 7 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆52Updated last week
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- ☆21Updated 9 years ago