hdl / bazel_rules_hdl
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
☆129Updated 2 weeks ago
Alternatives and similar repositories for bazel_rules_hdl:
Users that are interested in bazel_rules_hdl are comparing it to the libraries listed below
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆217Updated 3 weeks ago
- A dependency management tool for hardware projects.☆292Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆313Updated this week
- SystemVerilog synthesis tool☆189Updated last month
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- FPGA tool performance profiling☆102Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆57Updated 3 months ago
- ☆92Updated last year
- FuseSoC standard core library☆133Updated 3 weeks ago
- ☆77Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆388Updated last week
- Generic Register Interface (contains various adapters)☆113Updated 7 months ago
- Control and status register code generator toolchain☆123Updated last month
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆63Updated 2 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- Fabric generator and CAD tools☆177Updated last week
- Announcements related to Verilator☆39Updated 4 years ago
- SystemRDL 2.0 language compiler front-end☆251Updated last month
- A complete open-source design-for-testing (DFT) Solution☆147Updated 5 months ago
- Hardware generator debugger☆73Updated last year
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆277Updated this week
- Bazel build rules for compiling Verilog☆21Updated last year
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆58Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆113Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated this week
- ☆31Updated last year
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆95Updated 2 weeks ago
- ideas and eda software for vlsi design☆50Updated this week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 10 months ago