Alternatives and similar repositories for bazel_rules_hdl

Users that are interested in bazel_rules_hdl are comparing it to the libraries listed below

• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆332Updated this week
• pieter3d / simview
  ☆85Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆216Updated 7 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆160Updated last week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 5 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆261Updated last month
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆109Updated 11 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆168Updated this week
• Lightelligence / rules_verilog
  Bazel build rules for compiling Verilog
  ☆21Updated last year
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆116Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆64Updated 9 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 3 weeks ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆288Updated 2 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆345Updated last week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆57Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆65Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆128Updated last month
• chipsalliance / VeeR-ISS
  ☆149Updated 2 years ago
• tymonx / logic
  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
  ☆282Updated 5 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆201Updated last week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆226Updated last year
• chipsalliance / uvm-verilator
  ☆99Updated 2 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆167Updated 2 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆41Updated 5 years ago