Alternatives and similar repositories for bazel_rules_hdl

Users that are interested in bazel_rules_hdl are comparing it to the libraries listed below

• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆245Updated 4 months ago
• Lightelligence / rules_verilog
  Bazel build rules for compiling Verilog
  ☆21Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆225Updated 10 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆270Updated 2 weeks ago
• pieter3d / simview
  ☆89Updated 3 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆343Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆191Updated last week
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆105Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆132Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆135Updated this week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆109Updated last week
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆119Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆300Updated last week
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆121Updated 4 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated 2 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆438Updated 4 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆60Updated 2 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆356Updated last week
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆111Updated 3 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated last week
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆254Updated 4 months ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆148Updated 3 weeks ago