hdl / bazel_rules_hdl
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
☆119Updated this week
Related projects ⓘ
Alternatives and complementary repositories for bazel_rules_hdl
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆202Updated last week
- Bazel build rules for compiling Verilog☆21Updated 8 months ago
- ☆76Updated 8 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Python bindings for slang, a library for compiling SystemVerilog☆46Updated this week
- Control and status register code generator toolchain☆105Updated 2 months ago
- A SystemVerilog source file pickler.☆51Updated last month
- WAL enables programmable waveform analysis.☆138Updated 3 weeks ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆53Updated 4 months ago
- Test suite designed to check compliance with the SystemVerilog standard.☆297Updated this week
- FuseSoC standard core library☆115Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆47Updated 2 months ago
- A dependency management tool for hardware projects.☆251Updated last month
- SystemVerilog synthesis tool☆169Updated this week
- Fabric generator and CAD tools☆148Updated last week
- FPGA tool performance profiling☆102Updated 8 months ago
- SystemRDL 2.0 language compiler front-end☆236Updated 2 months ago
- SystemVerilog grammar for tree-sitter☆93Updated last week
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆368Updated last week
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆255Updated last week
- ☆30Updated last year
- Announcements related to Verilator☆38Updated 4 years ago
- Constrained random stimuli generation for C++ and SystemC☆49Updated 11 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆32Updated last month
- Python packages providing a library for Verification Stimulus and Coverage☆114Updated 2 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆70Updated last month
- 👾 Design ∪ Hardware☆72Updated 2 weeks ago
- A JSON library implemented in VHDL.☆76Updated 2 years ago