hdl / bazel_rules_hdl

Related projects ⓘ

Alternatives and complementary repositories for bazel_rules_hdl

• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆201Updated last month
• pieter3d / simview
  ☆76Updated 8 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆101Updated 8 months ago
• Lightelligence / rules_verilog
  Bazel build rules for compiling Verilog
  ☆21Updated 8 months ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆233Updated 2 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆93Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆168Updated this week
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆45Updated last week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆81Updated 5 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆295Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆113Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆101Updated 2 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆51Updated 3 weeks ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆109Updated last year
• sifive / duh
  👾 Design ∪ Hardware
  ☆72Updated last week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆363Updated this week
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆54Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆114Updated 3 weeks ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆136Updated 2 weeks ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆76Updated 2 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆71Updated 2 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆52Updated 3 months ago
• slaclab / ruckus
  Vivado build system
  ☆70Updated last month
• FPGA-Research-Manchester / FABulous
  Fabric generator and CAD tools
  ☆148Updated this week
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆107Updated last month
• chipsalliance / uvm-verilator
  ☆73Updated last year
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆127Updated 2 weeks ago
• chipsalliance / AIB-specification
  Home of the Advanced Interface Bus (AIB) specification.
  ☆49Updated 2 years ago