Alternatives and similar repositories for HiFi-DRAM:

Users that are interested in HiFi-DRAM are comparing it to the libraries listed below

• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆32Updated this week
• rahulk29 / sram22
  A configurable SRAM generator
  ☆42Updated 3 weeks ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆20Updated last week
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆34Updated 2 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated 2 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• aolofsson / POSH
  ☆40Updated 5 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated last year
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆30Updated last year
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆38Updated 2 years ago
• icgrp / hipr
  ☆15Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆99Updated 9 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• PrincetonUniversity / MosaicSim
  Heterogeneous simulator for DECADES Project
  ☆31Updated 8 months ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆48Updated last year
• chipsalliance / fpga-interchange-schema
  ☆53Updated 2 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆43Updated last year
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆38Updated last year
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆21Updated last week
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆23Updated last year
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆40Updated 4 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆16Updated 4 years ago
• aolofsson / IDEA
  ☆32Updated 5 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆23Updated 9 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆62Updated 4 years ago
• PrincetonUniversity / OPDB
  OpenPiton Design Benchmark
  ☆24Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆40Updated 2 months ago