comsec-group / HiFi-DRAMLinks
This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifiers with IC Imaging
☆20Updated last year
Alternatives and similar repositories for HiFi-DRAM
Users that are interested in HiFi-DRAM are comparing it to the libraries listed below
Sorting:
- ☆44Updated 5 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Library of open source Process Design Kits (PDKs)☆42Updated this week
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 6 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆13Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- ☆33Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated 2 weeks ago
- Fast Symbolic Repair of Hardware Design Code☆23Updated 4 months ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 4 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 7 months ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- A configurable SRAM generator☆50Updated last week
- sram/rram/mram.. compiler☆35Updated last year
- Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.☆33Updated last year
- ☆31Updated 2 years ago
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆17Updated 4 years ago
- ☆18Updated 11 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Source files to reproduce the results shown for A-QED at DAC 2020☆9Updated 4 years ago
- ☆25Updated 2 years ago
- ILP SAT Detailed Router☆11Updated 5 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆110Updated last year
- An infrastructure for integrated EDA☆41Updated last year
- ☆20Updated 3 years ago
- Equivalence checking with Yosys☆43Updated last month
- An automatic clock gating utility☆48Updated last month
- Characterizer☆23Updated 2 weeks ago