Alternatives and similar repositories for X-Cache:

Users that are interested in X-Cache are comparing it to the libraries listed below

• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• PolyArch / gem-forge-framework
  ☆24Updated last year
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆31Updated last year
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• CMU-SAFARI / Load-Inspector
  A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…
  ☆20Updated 8 months ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆17Updated 10 months ago
• cucapra / EventQueue
  EQueue Dialect
  ☆40Updated 3 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆62Updated 8 months ago
• hngenc / stellar
  ☆22Updated 3 months ago
• pku-liang / ksim
  ☆39Updated last month
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆58Updated 4 months ago
• bsc-mem / Mess-simulator
  A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.
  ☆20Updated 2 months ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆45Updated 2 weeks ago
• icgrp / pld2022
  ☆15Updated 2 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆91Updated last year
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆20Updated 10 months ago
• EECS-NTNU / chipyard
  Pre-release starter template for custom Chisel projects
  ☆9Updated 5 months ago
• ConvolutedDog / HyFiSS
  HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
  ☆26Updated 2 months ago
• suchandler96 / gem5-NVDLA
  ☆28Updated 5 months ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆41Updated 7 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆30Updated 3 years ago
• stanford-ppl / DAM-RS
  ☆17Updated 3 weeks ago
• pku-liang / hestia
  ☆12Updated last month
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆68Updated 5 years ago
• UCLA-VAST / hbmbench
  ☆23Updated 4 years ago
• he-actlab / planaria.code
  ☆25Updated 3 years ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆120Updated last year
• Yinxiao-Feng / chiplet-network-sim
  ☆26Updated 2 months ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆47Updated 2 months ago