Alternatives and similar repositories for X-Cache

Users that are interested in X-Cache are comparing it to the libraries listed below

• PolyArch / gem-forge-framework
  ☆26Updated 2 years ago
• TeCSAR-UNCC / gem5-SALAM
  ☆101Updated last year
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 3 years ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆34Updated last year
• cucapra / EventQueue
  EQueue Dialect
  ☆39Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆78Updated 6 years ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆71Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆120Updated 2 years ago
• hngenc / stellar
  ☆32Updated 11 months ago
• CMU-SAFARI / Load-Inspector
  A binary instrumentation tool to analyze load instructions in any off-the-shelf x86(-64) program. Described by Bera et al. in https://arx…
  ☆22Updated last year
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆59Updated 6 months ago
• cdsc-github / parade-ara-simulator
  PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration
  ☆49Updated 3 years ago
• ConvolutedDog / HyFiSS
  HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs
  ☆36Updated 10 months ago
• Systems-ShiftLab / MultiPIM
  MultiPIM: A Detailed and Configurable Multi-Stack Processing-In-Memory Simulator
  ☆56Updated 4 years ago
• stonne-simulator / sst-elements-with-stonne
  STONNE Simulator integrated into SST Simulator
  ☆21Updated last year
• cornell-zhang / allo-pldi24-artifact
  Artifact evaluation of PLDI'24 paper "Allo: A Programming Model for Composable Accelerator Design"
  ☆29Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆66Updated 4 years ago
• bsc-mem / Mess-simulator
  A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.
  ☆26Updated 2 months ago
• pku-liang / HASCO
  agile hardware-software co-design
  ☆52Updated 3 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆83Updated 2 years ago
• pku-liang / ksim
  ☆47Updated 9 months ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆65Updated 10 months ago
• GramThanos / CPU-on-Vivado-HLS
  A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS
  ☆18Updated 6 years ago
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆75Updated last month
• he-actlab / planaria.code
  ☆29Updated 3 years ago