rodrigomelo9 / verifying-foss-hdl-synthesizersLinks
a project to check the FOSS synthesizers against vendors EDA tools
☆12Updated 5 years ago
Alternatives and similar repositories for verifying-foss-hdl-synthesizers
Users that are interested in verifying-foss-hdl-synthesizers are comparing it to the libraries listed below
Sorting:
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Generate symbols from HDL components/modules☆22Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆49Updated 3 years ago
- Library of reusable VHDL components☆28Updated last year
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Updated 4 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Use XML files to describe register maps; auto-generate C, VHDL, Python, and HTML.☆13Updated 4 months ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Updated last year
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Updated 9 months ago
- A VHDL Core Library.☆18Updated 8 years ago
- VHDL String Formatting Library☆27Updated last year
- VHDL dependency analyzer☆24Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- VHDL related news.☆27Updated this week
- cocotb extension for nMigen☆17Updated 3 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Updated 7 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆53Updated 3 weeks ago
- LunaPnR is a place and router for integrated circuits☆47Updated 6 months ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- ☆13Updated 4 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago