KULeuven-MICAS / snax_clusterLinks
A heterogeneous accelerator-centric compute cluster
☆17Updated this week
Alternatives and similar repositories for snax_cluster
Users that are interested in snax_cluster are comparing it to the libraries listed below
Sorting:
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated last month
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- ☆28Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- RTL implementation of Flex-DPE.☆100Updated 5 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- Model LLM inference on single-core dataflow accelerators☆10Updated 3 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Library of approximate arithmetic circuits☆54Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- A collection of research papers on SRAM-based compute-in-memory architectures.☆28Updated last year
- Open-source of MSD framework☆16Updated last year
- ☆111Updated 4 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆39Updated 2 years ago
- ☆16Updated 3 weeks ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆71Updated 2 years ago
- ☆27Updated 2 months ago
- ☆44Updated 2 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆28Updated 8 months ago
- Verilog implementation of Softmax function☆66Updated 2 years ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- ☆65Updated 6 years ago
- ☆33Updated 6 years ago
- An FPGA Accelerator for Transformer Inference☆82Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆36Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year