A heterogeneous accelerator-centric compute cluster
☆69Nov 5, 2026Updated this week
Alternatives and similar repositories for snax_cluster
Users that are interested in snax_cluster are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆22Jul 1, 2024Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆72Updated this week
- Driving Snax with MLIR☆26Apr 22, 2026Updated 6 months ago
- Model LLM inference on single-core dataflow accelerators☆22Dec 16, 2025Updated 10 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆207Oct 11, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HW accelerator mapping optimization framework for in-memory computing☆30Jun 3, 2025Updated last year
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆44Feb 8, 2023Updated 3 years ago
- Zeonica is a simulator for CGRA and Wafer-Scale Accelerators.☆23Updated this week
- GEMM and GEMM-Ops accelerator for PULP systems☆126Updated this week
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆17Oct 14, 2026Updated 3 weeks ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆57Oct 31, 2025Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆126Nov 26, 2025Updated 11 months ago
- ☆28Apr 17, 2026Updated 6 months ago
- ☆13Jun 12, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Berkeley's Spatial Array Generator☆1,559Updated this week
- PCCX v002 KV260 board/model integration and verification, consuming a pinned reusable core. Operated by Altifigence.☆21Sep 27, 2026Updated last month
- An RTL-level, Chipyard-compatible DRAM simulator model for high fidelity memory simulations.☆13Jan 4, 2026Updated 10 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆89Sep 29, 2025Updated last year
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago
- ☆57Updated this week
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆17Sep 18, 2026Updated last month
- TAIDL: Tensor Accelerator ISA Definition Language☆25Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework☆149Updated this week
- A Cycle-level simulator for M2NDP☆48Aug 14, 2025Updated last year
- RTL for AXI over UCIe bridge.☆45Updated this week
- ☆13May 10, 2018Updated 8 years ago
- ☆37Oct 12, 2026Updated 3 weeks ago
- A flexible, high-performance, user-friendly computer architecture simulator engine☆123Updated this week
- ☆14Aug 24, 2026Updated 2 months ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆219Oct 23, 2026Updated 2 weeks ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆69Oct 9, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆19Apr 23, 2025Updated last year
- eXtensible Heterogeneous Energy-Efficient Platform based on RISC-V☆309Updated this week
- Synthesisable SIMT-style RISC-V GPGPU☆59Mar 30, 2026Updated 7 months ago
- A hardware accelerator for General Matrix Multiply, developed in SystemC using ESP.☆21May 26, 2021Updated 5 years ago
- An open-hardware co-design framework for deploying PyTorch models on RISC-V SoCs with custom ML accelerators, enabling rapid design spac…☆15Feb 12, 2025Updated last year
- RISC-V-based many-core neuromorphic architecture☆19Oct 28, 2026Updated last week
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆68Sep 24, 2021Updated 5 years ago