The-OpenROAD-Project / micro2022tutorial
Website for the OpenROAD tutorial held at the MICRO 2022 conference
☆25Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for micro2022tutorial
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆95Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆117Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆93Updated 7 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆65Updated 3 months ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆21Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆93Updated this week
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆52Updated 2 weeks ago
- ☆39Updated 4 years ago
- Tutorials on HLS Design☆49Updated 4 years ago
- ☆87Updated 8 months ago
- ☆47Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆33Updated last year
- ☆100Updated 4 months ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆156Updated this week
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆85Updated last year
- IC implementation of TPU☆86Updated 4 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆64Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month