The-OpenROAD-Project / micro2022tutorialLinks
Website for the OpenROAD tutorial held at the MICRO 2022 conference
☆28Updated 2 years ago
Alternatives and similar repositories for micro2022tutorial
Users that are interested in micro2022tutorial are comparing it to the libraries listed below
Sorting:
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆56Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- ☆15Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- ☆50Updated 6 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆110Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆44Updated 8 months ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- ☆58Updated 4 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated this week
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆83Updated last year
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆67Updated last year
- Next generation CGRA generator☆111Updated last week
- ☆86Updated last year
- Tutorials on HLS Design☆51Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- Logic synthesis and ABC based optimization☆49Updated 3 weeks ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- ☆59Updated last month
- Basic floating-point components for RISC-V processors☆65Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago