Website for the OpenROAD tutorial held at the MICRO 2022 conference
☆36Oct 6, 2022Updated 3 years ago
Alternatives and similar repositories for micro2022tutorial
Users that are interested in micro2022tutorial are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆11Mar 4, 2025Updated last year
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆21Aug 10, 2023Updated 3 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 5 years ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆703Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Light modbus RTU Slave without SPL and HAL. This lib doesn't need timers, only UART and 2 channels of DMA.☆10Jun 25, 2019Updated 7 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆36Jun 30, 2020Updated 6 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆55Jan 19, 2025Updated last year
- Open source Photonics PDK for VTT's 3 um SOI platform.☆14Updated this week
- ☆27Aug 2, 2021Updated 5 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆45Jun 16, 2025Updated last year
- Replace Tcl scripting with Python☆18Apr 3, 2026Updated 4 months ago
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 7 months ago
- All Digital Phase-Locked Loop (ADPLL)☆38Jan 16, 2024Updated 2 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆59Nov 16, 2023Updated 2 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- An open source PDK using TIGFET 10nm devices.☆60Dec 19, 2022Updated 3 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- The best rtl_uart in github! This is a UART design based on AXI Stream/Ready Vallid protocol. Support parameterized data bit width, clock…☆11May 8, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆41May 17, 2024Updated 2 years ago
- A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…☆47Updated this week
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- ☆27Jul 27, 2017Updated 9 years ago
- Working on a Performance Analyser using ImGui☆12Aug 31, 2017Updated 8 years ago
- Open FPGA Modules☆26Oct 8, 2024Updated last year
- ☆10Apr 4, 2024Updated 2 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆79Jul 31, 2018Updated 8 years ago
- 12 bit SAR ADC for TinyTapeout 7☆15May 30, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- ☆17Jul 30, 2021Updated 5 years ago
- ☆15Nov 12, 2023Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Jun 28, 2025Updated last year
- gdsfactory implementation of LXT PDK.☆23Updated this week
- An open-source static random access memory (SRAM) compiler.☆1,113Jul 18, 2026Updated 3 weeks ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆155Mar 19, 2018Updated 8 years ago