Website for the OpenROAD tutorial held at the MICRO 2022 conference
☆35Oct 6, 2022Updated 3 years ago
Alternatives and similar repositories for micro2022tutorial
Users that are interested in micro2022tutorial are comparing it to the libraries listed below
Sorting:
- ☆11Mar 4, 2025Updated last year
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆20Aug 10, 2023Updated 2 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0☆14Oct 4, 2022Updated 3 years ago
- Examples from the Openlane repository, adapted as Fusesoc cores☆12May 18, 2021Updated 4 years ago
- Datasets for EDA LLM research☆38Jan 17, 2025Updated last year
- Light modbus RTU Slave without SPL and HAL. This lib doesn't need timers, only UART and 2 channels of DMA.☆10Jun 25, 2019Updated 6 years ago
- OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/☆590Mar 14, 2026Updated last week
- ☆27Aug 2, 2021Updated 4 years ago
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆54Jan 19, 2025Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆44Jun 16, 2025Updated 9 months ago
- gdsfactory implementation of LXT PDK.☆18Mar 13, 2026Updated last week
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆55Nov 16, 2023Updated 2 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆14Mar 17, 2019Updated 7 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆37Nov 6, 2025Updated 4 months ago
- An open source PDK using TIGFET 10nm devices.☆56Dec 19, 2022Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆38Mar 11, 2026Updated last week
- Working on a Performance Analyser using ImGui☆12Aug 31, 2017Updated 8 years ago
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- ☆26Jul 27, 2017Updated 8 years ago
- LLM-Aided FPGA Design for Signal Processing Applications☆33Jun 4, 2025Updated 9 months ago
- SmoothE: Differentiable E-Graph Extraction (ASPLOS'25 Best Paper)☆31Jan 15, 2026Updated 2 months ago
- Open FPGA Modules☆24Oct 8, 2024Updated last year
- matrix-coprocessor for RISC-V☆31Feb 27, 2026Updated 3 weeks ago
- ☆15Jul 30, 2021Updated 4 years ago
- design and verification of asynchronous circuits☆44Feb 27, 2026Updated 3 weeks ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆53Jan 4, 2022Updated 4 years ago
- ☆18May 5, 2022Updated 3 years ago
- A paper review list for computer architecture and systems research, maintained by the LEMONADE group at Peking University.☆16Mar 12, 2026Updated last week
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 11 years ago
- An open-source static random access memory (SRAM) compiler.☆1,021Mar 12, 2026Updated last week
- The hardware implementation of UDP in Bluespec SystemVerilog☆14Jun 3, 2024Updated last year
- MBLANC: mini Board Lab and Companion☆11Jan 5, 2023Updated 3 years ago
- Open Source Reinforcement Learning Framework for Routing and Spectrum Assignment☆10Mar 18, 2021Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆147Mar 19, 2018Updated 8 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆22Dec 20, 2019Updated 6 years ago