Alternatives and similar repositories for verilog-parser

Users that are interested in verilog-parser are comparing it to the libraries listed below

• ben-marshall / verilog-vcd-parser
  A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
  ☆100Updated 3 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆167Updated 2 months ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆237Updated 2 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆168Updated last week
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆263Updated last month
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆308Updated 4 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆423Updated 2 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆216Updated 8 months ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆62Updated last year
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆129Updated last month
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 9 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆346Updated last week
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 4 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆185Updated this week
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆300Updated 3 weeks ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆143Updated last year
• chipsalliance / uvm-verilator
  ☆103Updated this week
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆226Updated this week
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆236Updated last week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆179Updated 10 months ago
• subbdue / systemverilog.io
  Code used in
  ☆198Updated 8 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆111Updated last week
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 2 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated this week
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated 3 weeks ago
• eirikpre / VSCode-SystemVerilog
  SystemVerilog support in VS Code
  ☆143Updated 8 months ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆82Updated last year
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆125Updated last year