A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
☆135Jul 17, 2019Updated 6 years ago
Alternatives and similar repositories for verilog-parser
Users that are interested in verilog-parser are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 9 years ago
- A verilog parser☆19Apr 12, 2024Updated last year
- A Standalone Structural Verilog Parser☆99Mar 31, 2022Updated 3 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆451Mar 8, 2026Updated 2 weeks ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 9 years ago
- Python-based Verilog Parser (currently Netlist only)☆54Apr 12, 2017Updated 8 years ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆778Jun 15, 2024Updated last year
- This is the Verilog 2005 parser used by VerilogCreator☆15May 19, 2019Updated 6 years ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆467Nov 4, 2025Updated 4 months ago
- ☆15Oct 24, 2019Updated 6 years ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4☆320Jun 30, 2025Updated 8 months ago
- ☆105Jun 27, 2022Updated 3 years ago
- SystemVerilog compiler and language services☆989Updated this week
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 9 months ago
- UCSD Detailed Router☆95Jan 5, 2021Updated 5 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,132Mar 11, 2026Updated 2 weeks ago
- OpenSTA engine☆557Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,789Mar 13, 2026Updated last week
- Read-only release history for Verilog-Perl☆14Jan 8, 2015Updated 11 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆142Mar 20, 2023Updated 3 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Nov 1, 2022Updated 3 years ago
- Mirror of Synopsys's Liberty parser library☆24Jul 6, 2018Updated 7 years ago
- ☆13Jun 22, 2017Updated 8 years ago
- ☆11Jul 1, 2025Updated 8 months ago
- Open source EDA chip design flow☆51Mar 15, 2017Updated 9 years ago
- Simple Verilog Parser In Python☆15Dec 31, 2017Updated 8 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- UCSD Sizer for leakage/dynamic power recovery, timing recovery☆18Mar 5, 2019Updated 7 years ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆103Mar 6, 2022Updated 4 years ago
- ILP SAT Detailed Router☆13Apr 14, 2020Updated 5 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆233Updated this week
- Workshop on Open-Source EDA Technology (WOSET)☆48Nov 18, 2024Updated last year
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19May 29, 2018Updated 7 years ago
- Yosys Open SYnthesis Suite☆4,348Updated this week
- SystemVerilog to Verilog conversion☆709Nov 24, 2025Updated 4 months ago